1 /* 2 * Copyright 2008 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/immap_fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 39 #include "../common/pixis.h" 40 41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 42 extern void ddr_enable_ecc(unsigned int dram_size); 43 #endif 44 45 phys_size_t fixed_sdram(void); 46 47 int checkboard (void) 48 { 49 printf ("Board: MPC8536DS, System ID: 0x%02x, " 50 "System Version: 0x%02x, FPGA Version: 0x%02x\n", 51 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), 52 in8(PIXIS_BASE + PIXIS_PVER)); 53 return 0; 54 } 55 56 phys_size_t 57 initdram(int board_type) 58 { 59 phys_size_t dram_size = 0; 60 61 puts("Initializing...."); 62 63 #ifdef CONFIG_SPD_EEPROM 64 dram_size = fsl_ddr_sdram(); 65 66 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 67 68 dram_size *= 0x100000; 69 #else 70 dram_size = fixed_sdram(); 71 #endif 72 73 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 74 /* 75 * Initialize and enable DDR ECC. 76 */ 77 ddr_enable_ecc(dram_size); 78 #endif 79 puts(" DDR: "); 80 return dram_size; 81 } 82 83 #if !defined(CONFIG_SPD_EEPROM) 84 /* 85 * Fixed sdram init -- doesn't use serial presence detect. 86 */ 87 88 phys_size_t fixed_sdram (void) 89 { 90 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 91 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 92 uint d_init; 93 94 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 95 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 96 97 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 98 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 99 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 100 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 101 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 102 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 103 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 104 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 105 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 106 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 107 108 #if defined (CONFIG_DDR_ECC) 109 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 110 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 111 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 112 #endif 113 asm("sync;isync"); 114 115 udelay(500); 116 117 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 118 119 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 120 d_init = 1; 121 debug("DDR - 1st controller: memory initializing\n"); 122 /* 123 * Poll until memory is initialized. 124 * 512 Meg at 400 might hit this 200 times or so. 125 */ 126 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 127 udelay(1000); 128 } 129 debug("DDR: memory initialized\n\n"); 130 asm("sync; isync"); 131 udelay(500); 132 #endif 133 134 return 512 * 1024 * 1024; 135 } 136 137 #endif 138 139 #ifdef CONFIG_PCI1 140 static struct pci_controller pci1_hose; 141 #endif 142 143 #ifdef CONFIG_PCIE1 144 static struct pci_controller pcie1_hose; 145 #endif 146 147 #ifdef CONFIG_PCIE2 148 static struct pci_controller pcie2_hose; 149 #endif 150 151 #ifdef CONFIG_PCIE3 152 static struct pci_controller pcie3_hose; 153 #endif 154 155 int first_free_busno=0; 156 157 void 158 pci_init_board(void) 159 { 160 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 161 uint devdisr = gur->devdisr; 162 uint sdrs2_io_sel = 163 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 164 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 165 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 166 167 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 168 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 169 170 if (sdrs2_io_sel == 7) 171 printf(" Serdes2 disalbed\n"); 172 else if (sdrs2_io_sel == 4) { 173 printf(" eTSEC1 is in sgmii mode.\n"); 174 printf(" eTSEC3 is in sgmii mode.\n"); 175 } else if (sdrs2_io_sel == 6) 176 printf(" eTSEC1 is in sgmii mode.\n"); 177 178 #ifdef CONFIG_PCIE3 179 { 180 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 181 extern void fsl_pci_init(struct pci_controller *hose); 182 struct pci_controller *hose = &pcie3_hose; 183 int pcie_ep = (host_agent == 1); 184 int pcie_configured = (io_sel == 7); 185 186 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 187 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 188 pcie_ep ? "End Point" : "Root Complex", 189 (uint)pci); 190 if (pci->pme_msg_det) { 191 pci->pme_msg_det = 0xffffffff; 192 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 193 } 194 printf ("\n"); 195 196 /* inbound */ 197 pci_set_region(hose->regions + 0, 198 CONFIG_SYS_PCI_MEMORY_BUS, 199 CONFIG_SYS_PCI_MEMORY_PHYS, 200 CONFIG_SYS_PCI_MEMORY_SIZE, 201 PCI_REGION_MEM | PCI_REGION_MEMORY); 202 203 /* outbound memory */ 204 pci_set_region(hose->regions + 1, 205 CONFIG_SYS_PCIE3_MEM_BASE, 206 CONFIG_SYS_PCIE3_MEM_PHYS, 207 CONFIG_SYS_PCIE3_MEM_SIZE, 208 PCI_REGION_MEM); 209 210 /* outbound io */ 211 pci_set_region(hose->regions + 2, 212 CONFIG_SYS_PCIE3_IO_BASE, 213 CONFIG_SYS_PCIE3_IO_PHYS, 214 CONFIG_SYS_PCIE3_IO_SIZE, 215 PCI_REGION_IO); 216 217 hose->region_count = 3; 218 219 hose->first_busno=first_free_busno; 220 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 221 222 fsl_pci_init(hose); 223 224 first_free_busno=hose->last_busno+1; 225 printf (" PCIE3 on bus %02x - %02x\n", 226 hose->first_busno,hose->last_busno); 227 } else { 228 printf (" PCIE3: disabled\n"); 229 } 230 231 } 232 #else 233 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 234 #endif 235 236 #ifdef CONFIG_PCIE1 237 { 238 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 239 extern void fsl_pci_init(struct pci_controller *hose); 240 struct pci_controller *hose = &pcie1_hose; 241 int pcie_ep = (host_agent == 5); 242 int pcie_configured = (io_sel == 2 || io_sel == 3 243 || io_sel == 5 || io_sel == 7); 244 245 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 246 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 247 pcie_ep ? "End Point" : "Root Complex", 248 (uint)pci); 249 if (pci->pme_msg_det) { 250 pci->pme_msg_det = 0xffffffff; 251 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 252 } 253 printf ("\n"); 254 255 /* inbound */ 256 pci_set_region(hose->regions + 0, 257 CONFIG_SYS_PCI_MEMORY_BUS, 258 CONFIG_SYS_PCI_MEMORY_PHYS, 259 CONFIG_SYS_PCI_MEMORY_SIZE, 260 PCI_REGION_MEM | PCI_REGION_MEMORY); 261 262 /* outbound memory */ 263 pci_set_region(hose->regions + 1, 264 CONFIG_SYS_PCIE1_MEM_BASE, 265 CONFIG_SYS_PCIE1_MEM_PHYS, 266 CONFIG_SYS_PCIE1_MEM_SIZE, 267 PCI_REGION_MEM); 268 269 /* outbound io */ 270 pci_set_region(hose->regions + 2, 271 CONFIG_SYS_PCIE1_IO_BASE, 272 CONFIG_SYS_PCIE1_IO_PHYS, 273 CONFIG_SYS_PCIE1_IO_SIZE, 274 PCI_REGION_IO); 275 276 hose->region_count = 3; 277 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2 278 /* outbound memory */ 279 pci_set_region(hose->regions + 3, 280 CONFIG_SYS_PCIE1_MEM_BASE2, 281 CONFIG_SYS_PCIE1_MEM_PHYS2, 282 CONFIG_SYS_PCIE1_MEM_SIZE2, 283 PCI_REGION_MEM); 284 hose->region_count++; 285 #endif 286 hose->first_busno=first_free_busno; 287 288 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 289 290 fsl_pci_init(hose); 291 292 first_free_busno=hose->last_busno+1; 293 printf(" PCIE1 on bus %02x - %02x\n", 294 hose->first_busno,hose->last_busno); 295 296 } else { 297 printf (" PCIE1: disabled\n"); 298 } 299 300 } 301 #else 302 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 303 #endif 304 305 #ifdef CONFIG_PCIE2 306 { 307 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 308 extern void fsl_pci_init(struct pci_controller *hose); 309 struct pci_controller *hose = &pcie2_hose; 310 int pcie_ep = (host_agent == 3); 311 int pcie_configured = (io_sel == 5 || io_sel == 7); 312 313 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 314 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 315 pcie_ep ? "End Point" : "Root Complex", 316 (uint)pci); 317 if (pci->pme_msg_det) { 318 pci->pme_msg_det = 0xffffffff; 319 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 320 } 321 printf ("\n"); 322 323 /* inbound */ 324 pci_set_region(hose->regions + 0, 325 CONFIG_SYS_PCI_MEMORY_BUS, 326 CONFIG_SYS_PCI_MEMORY_PHYS, 327 CONFIG_SYS_PCI_MEMORY_SIZE, 328 PCI_REGION_MEM | PCI_REGION_MEMORY); 329 330 /* outbound memory */ 331 pci_set_region(hose->regions + 1, 332 CONFIG_SYS_PCIE2_MEM_BASE, 333 CONFIG_SYS_PCIE2_MEM_PHYS, 334 CONFIG_SYS_PCIE2_MEM_SIZE, 335 PCI_REGION_MEM); 336 337 /* outbound io */ 338 pci_set_region(hose->regions + 2, 339 CONFIG_SYS_PCIE2_IO_BASE, 340 CONFIG_SYS_PCIE2_IO_PHYS, 341 CONFIG_SYS_PCIE2_IO_SIZE, 342 PCI_REGION_IO); 343 344 hose->region_count = 3; 345 #ifdef CONFIG_SYS_PCIE2_MEM_BASE2 346 /* outbound memory */ 347 pci_set_region(hose->regions + 3, 348 CONFIG_SYS_PCIE2_MEM_BASE2, 349 CONFIG_SYS_PCIE2_MEM_PHYS2, 350 CONFIG_SYS_PCIE2_MEM_SIZE2, 351 PCI_REGION_MEM); 352 hose->region_count++; 353 #endif 354 hose->first_busno=first_free_busno; 355 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 356 357 fsl_pci_init(hose); 358 first_free_busno=hose->last_busno+1; 359 printf (" PCIE2 on bus %02x - %02x\n", 360 hose->first_busno,hose->last_busno); 361 362 } else { 363 printf (" PCIE2: disabled\n"); 364 } 365 366 } 367 #else 368 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 369 #endif 370 371 372 #ifdef CONFIG_PCI1 373 { 374 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 375 extern void fsl_pci_init(struct pci_controller *hose); 376 struct pci_controller *hose = &pci1_hose; 377 378 uint pci_agent = (host_agent == 6); 379 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 380 uint pci_32 = 1; 381 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 382 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 383 384 385 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 386 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 387 (pci_32) ? 32 : 64, 388 (pci_speed == 33333000) ? "33" : 389 (pci_speed == 66666000) ? "66" : "unknown", 390 pci_clk_sel ? "sync" : "async", 391 pci_agent ? "agent" : "host", 392 pci_arb ? "arbiter" : "external-arbiter", 393 (uint)pci 394 ); 395 396 /* inbound */ 397 pci_set_region(hose->regions + 0, 398 CONFIG_SYS_PCI_MEMORY_BUS, 399 CONFIG_SYS_PCI_MEMORY_PHYS, 400 CONFIG_SYS_PCI_MEMORY_SIZE, 401 PCI_REGION_MEM | PCI_REGION_MEMORY); 402 403 /* outbound memory */ 404 pci_set_region(hose->regions + 1, 405 CONFIG_SYS_PCI1_MEM_BASE, 406 CONFIG_SYS_PCI1_MEM_PHYS, 407 CONFIG_SYS_PCI1_MEM_SIZE, 408 PCI_REGION_MEM); 409 410 /* outbound io */ 411 pci_set_region(hose->regions + 2, 412 CONFIG_SYS_PCI1_IO_BASE, 413 CONFIG_SYS_PCI1_IO_PHYS, 414 CONFIG_SYS_PCI1_IO_SIZE, 415 PCI_REGION_IO); 416 hose->region_count = 3; 417 #ifdef CONFIG_SYS_PCI1_MEM_BASE2 418 /* outbound memory */ 419 pci_set_region(hose->regions + 3, 420 CONFIG_SYS_PCI1_MEM_BASE2, 421 CONFIG_SYS_PCI1_MEM_PHYS2, 422 CONFIG_SYS_PCI1_MEM_SIZE2, 423 PCI_REGION_MEM); 424 hose->region_count++; 425 #endif 426 hose->first_busno=first_free_busno; 427 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); 428 429 fsl_pci_init(hose); 430 first_free_busno=hose->last_busno+1; 431 printf ("PCI on bus %02x - %02x\n", 432 hose->first_busno,hose->last_busno); 433 } else { 434 printf (" PCI: disabled\n"); 435 } 436 } 437 #else 438 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 439 #endif 440 } 441 442 443 int board_early_init_r(void) 444 { 445 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 446 const u8 flash_esel = 1; 447 448 /* 449 * Remap Boot flash + PROMJET region to caching-inhibited 450 * so that flash can be erased properly. 451 */ 452 453 /* Flush d-cache and invalidate i-cache of any FLASH data */ 454 flush_dcache(); 455 invalidate_icache(); 456 457 /* invalidate existing TLB entry for flash + promjet */ 458 disable_tlb(flash_esel); 459 460 set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ 461 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 462 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 463 464 return 0; 465 } 466 467 #ifdef CONFIG_GET_CLK_FROM_ICS307 468 /* decode S[0-2] to Output Divider (OD) */ 469 static unsigned char 470 ics307_S_to_OD[] = { 471 10, 2, 8, 4, 5, 7, 3, 6 472 }; 473 474 /* Calculate frequency being generated by ICS307-02 clock chip based upon 475 * the control bytes being programmed into it. */ 476 /* XXX: This function should probably go into a common library */ 477 static unsigned long 478 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 479 { 480 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 481 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 482 unsigned long RDW = cw2 & 0x7F; 483 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 484 unsigned long freq; 485 486 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 487 488 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 489 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 490 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 491 * 492 * R6:R0 = Reference Divider Word (RDW) 493 * V8:V0 = VCO Divider Word (VDW) 494 * S2:S0 = Output Divider Select (OD) 495 * F1:F0 = Function of CLK2 Output 496 * TTL = duty cycle 497 * C1:C0 = internal load capacitance for cyrstal 498 */ 499 500 /* Adding 1 to get a "nicely" rounded number, but this needs 501 * more tweaking to get a "properly" rounded number. */ 502 503 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 504 505 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 506 freq); 507 return freq; 508 } 509 510 unsigned long 511 get_board_sys_clk(ulong dummy) 512 { 513 return ics307_clk_freq ( 514 in8(PIXIS_BASE + PIXIS_VSYSCLK0), 515 in8(PIXIS_BASE + PIXIS_VSYSCLK1), 516 in8(PIXIS_BASE + PIXIS_VSYSCLK2) 517 ); 518 } 519 520 unsigned long 521 get_board_ddr_clk(ulong dummy) 522 { 523 return ics307_clk_freq ( 524 in8(PIXIS_BASE + PIXIS_VDDRCLK0), 525 in8(PIXIS_BASE + PIXIS_VDDRCLK1), 526 in8(PIXIS_BASE + PIXIS_VDDRCLK2) 527 ); 528 } 529 #else 530 unsigned long 531 get_board_sys_clk(ulong dummy) 532 { 533 u8 i; 534 ulong val = 0; 535 536 i = in8(PIXIS_BASE + PIXIS_SPD); 537 i &= 0x07; 538 539 switch (i) { 540 case 0: 541 val = 33333333; 542 break; 543 case 1: 544 val = 40000000; 545 break; 546 case 2: 547 val = 50000000; 548 break; 549 case 3: 550 val = 66666666; 551 break; 552 case 4: 553 val = 83333333; 554 break; 555 case 5: 556 val = 100000000; 557 break; 558 case 6: 559 val = 133333333; 560 break; 561 case 7: 562 val = 166666666; 563 break; 564 } 565 566 return val; 567 } 568 569 unsigned long 570 get_board_ddr_clk(ulong dummy) 571 { 572 u8 i; 573 ulong val = 0; 574 575 i = in8(PIXIS_BASE + PIXIS_SPD); 576 i &= 0x38; 577 i >>= 3; 578 579 switch (i) { 580 case 0: 581 val = 33333333; 582 break; 583 case 1: 584 val = 40000000; 585 break; 586 case 2: 587 val = 50000000; 588 break; 589 case 3: 590 val = 66666666; 591 break; 592 case 4: 593 val = 83333333; 594 break; 595 case 5: 596 val = 100000000; 597 break; 598 case 6: 599 val = 133333333; 600 break; 601 case 7: 602 val = 166666666; 603 break; 604 } 605 return val; 606 } 607 #endif 608 609 int is_sata_supported(void) 610 { 611 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 612 uint devdisr = gur->devdisr; 613 uint sdrs2_io_sel = 614 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 615 if (sdrs2_io_sel & 0x04) 616 return 0; 617 618 return 1; 619 } 620 621 #if defined(CONFIG_OF_BOARD_SETUP) 622 void 623 ft_board_setup(void *blob, bd_t *bd) 624 { 625 int node, tmp[2]; 626 const char *path; 627 628 ft_cpu_setup(blob, bd); 629 630 node = fdt_path_offset(blob, "/aliases"); 631 tmp[0] = 0; 632 if (node >= 0) { 633 #ifdef CONFIG_PCI1 634 path = fdt_getprop(blob, node, "pci0", NULL); 635 if (path) { 636 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; 637 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 638 } 639 #endif 640 #ifdef CONFIG_PCIE2 641 path = fdt_getprop(blob, node, "pci1", NULL); 642 if (path) { 643 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; 644 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 645 } 646 #endif 647 #ifdef CONFIG_PCIE1 648 path = fdt_getprop(blob, node, "pci2", NULL); 649 if (path) { 650 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; 651 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 652 } 653 #endif 654 #ifdef CONFIG_PCIE3 655 path = fdt_getprop(blob, node, "pci3", NULL); 656 if (path) { 657 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; 658 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); 659 } 660 #endif 661 } 662 } 663 #endif 664