1 /* 2 * Copyright 2008 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 #include <tsec.h> 39 #include <netdev.h> 40 #include <sata.h> 41 42 #include "../common/pixis.h" 43 #include "../common/sgmii_riser.h" 44 45 phys_size_t fixed_sdram(void); 46 47 int board_early_init_f (void) 48 { 49 #ifdef CONFIG_MMC 50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 51 52 setbits_be32(&gur->pmuxcr, 53 (MPC85xx_PMUXCR_SD_DATA | 54 MPC85xx_PMUXCR_SDHC_CD | 55 MPC85xx_PMUXCR_SDHC_WP)); 56 57 #endif 58 return 0; 59 } 60 61 int checkboard (void) 62 { 63 u8 vboot; 64 u8 *pixis_base = (u8 *)PIXIS_BASE; 65 66 puts("Board: MPC8536DS "); 67 #ifdef CONFIG_PHYS_64BIT 68 puts("(36-bit addrmap) "); 69 #endif 70 71 printf ("Sys ID: 0x%02x, " 72 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 73 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 74 in_8(pixis_base + PIXIS_PVER)); 75 76 vboot = in_8(pixis_base + PIXIS_VBOOT); 77 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 78 case PIXIS_VBOOT_LBMAP_NOR0: 79 puts ("vBank: 0\n"); 80 break; 81 case PIXIS_VBOOT_LBMAP_NOR1: 82 puts ("vBank: 1\n"); 83 break; 84 case PIXIS_VBOOT_LBMAP_NOR2: 85 puts ("vBank: 2\n"); 86 break; 87 case PIXIS_VBOOT_LBMAP_NOR3: 88 puts ("vBank: 3\n"); 89 break; 90 case PIXIS_VBOOT_LBMAP_PJET: 91 puts ("Promjet\n"); 92 break; 93 case PIXIS_VBOOT_LBMAP_NAND: 94 puts ("NAND\n"); 95 break; 96 } 97 98 return 0; 99 } 100 101 phys_size_t 102 initdram(int board_type) 103 { 104 phys_size_t dram_size = 0; 105 106 puts("Initializing...."); 107 108 #ifdef CONFIG_SPD_EEPROM 109 dram_size = fsl_ddr_sdram(); 110 #else 111 dram_size = fixed_sdram(); 112 #endif 113 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 114 dram_size *= 0x100000; 115 116 puts(" DDR: "); 117 return dram_size; 118 } 119 120 #if !defined(CONFIG_SPD_EEPROM) 121 /* 122 * Fixed sdram init -- doesn't use serial presence detect. 123 */ 124 125 phys_size_t fixed_sdram (void) 126 { 127 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 128 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 129 uint d_init; 130 131 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 132 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 133 134 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 135 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 136 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 137 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 138 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 139 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 140 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 141 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 142 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 143 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 144 145 #if defined (CONFIG_DDR_ECC) 146 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 147 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 148 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 149 #endif 150 asm("sync;isync"); 151 152 udelay(500); 153 154 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 155 156 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 157 d_init = 1; 158 debug("DDR - 1st controller: memory initializing\n"); 159 /* 160 * Poll until memory is initialized. 161 * 512 Meg at 400 might hit this 200 times or so. 162 */ 163 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 164 udelay(1000); 165 } 166 debug("DDR: memory initialized\n\n"); 167 asm("sync; isync"); 168 udelay(500); 169 #endif 170 171 return 512 * 1024 * 1024; 172 } 173 174 #endif 175 176 #ifdef CONFIG_PCI1 177 static struct pci_controller pci1_hose; 178 #endif 179 180 #ifdef CONFIG_PCIE1 181 static struct pci_controller pcie1_hose; 182 #endif 183 184 #ifdef CONFIG_PCIE2 185 static struct pci_controller pcie2_hose; 186 #endif 187 188 #ifdef CONFIG_PCIE3 189 static struct pci_controller pcie3_hose; 190 #endif 191 192 int first_free_busno=0; 193 194 void 195 pci_init_board(void) 196 { 197 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 198 uint devdisr = gur->devdisr; 199 uint sdrs2_io_sel = 200 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 201 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 202 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 203 204 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 205 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 206 207 if (sdrs2_io_sel == 7) 208 printf(" Serdes2 disalbed\n"); 209 else if (sdrs2_io_sel == 4) { 210 printf(" eTSEC1 is in sgmii mode.\n"); 211 printf(" eTSEC3 is in sgmii mode.\n"); 212 } else if (sdrs2_io_sel == 6) 213 printf(" eTSEC1 is in sgmii mode.\n"); 214 215 #ifdef CONFIG_PCIE3 216 { 217 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 218 struct pci_controller *hose = &pcie3_hose; 219 int pcie_ep = (host_agent == 1); 220 int pcie_configured = (io_sel == 7); 221 struct pci_region *r = hose->regions; 222 223 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 224 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 225 pcie_ep ? "End Point" : "Root Complex", 226 (uint)pci); 227 if (pci->pme_msg_det) { 228 pci->pme_msg_det = 0xffffffff; 229 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 230 } 231 printf ("\n"); 232 233 /* outbound memory */ 234 pci_set_region(r++, 235 CONFIG_SYS_PCIE3_MEM_BUS, 236 CONFIG_SYS_PCIE3_MEM_PHYS, 237 CONFIG_SYS_PCIE3_MEM_SIZE, 238 PCI_REGION_MEM); 239 240 /* outbound io */ 241 pci_set_region(r++, 242 CONFIG_SYS_PCIE3_IO_BUS, 243 CONFIG_SYS_PCIE3_IO_PHYS, 244 CONFIG_SYS_PCIE3_IO_SIZE, 245 PCI_REGION_IO); 246 247 hose->region_count = r - hose->regions; 248 249 hose->first_busno=first_free_busno; 250 251 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 252 253 first_free_busno=hose->last_busno+1; 254 printf (" PCIE3 on bus %02x - %02x\n", 255 hose->first_busno,hose->last_busno); 256 } else { 257 printf (" PCIE3: disabled\n"); 258 } 259 260 } 261 #else 262 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 263 #endif 264 265 #ifdef CONFIG_PCIE1 266 { 267 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 268 struct pci_controller *hose = &pcie1_hose; 269 int pcie_ep = (host_agent == 5); 270 int pcie_configured = (io_sel == 2 || io_sel == 3 271 || io_sel == 5 || io_sel == 7); 272 struct pci_region *r = hose->regions; 273 274 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 275 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 276 pcie_ep ? "End Point" : "Root Complex", 277 (uint)pci); 278 if (pci->pme_msg_det) { 279 pci->pme_msg_det = 0xffffffff; 280 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 281 } 282 printf ("\n"); 283 284 /* outbound memory */ 285 pci_set_region(r++, 286 CONFIG_SYS_PCIE1_MEM_BUS, 287 CONFIG_SYS_PCIE1_MEM_PHYS, 288 CONFIG_SYS_PCIE1_MEM_SIZE, 289 PCI_REGION_MEM); 290 291 /* outbound io */ 292 pci_set_region(r++, 293 CONFIG_SYS_PCIE1_IO_BUS, 294 CONFIG_SYS_PCIE1_IO_PHYS, 295 CONFIG_SYS_PCIE1_IO_SIZE, 296 PCI_REGION_IO); 297 298 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 299 /* outbound memory */ 300 pci_set_region(r++, 301 CONFIG_SYS_PCIE1_MEM_BUS2, 302 CONFIG_SYS_PCIE1_MEM_PHYS2, 303 CONFIG_SYS_PCIE1_MEM_SIZE2, 304 PCI_REGION_MEM); 305 #endif 306 hose->region_count = r - hose->regions; 307 hose->first_busno=first_free_busno; 308 309 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 310 311 first_free_busno=hose->last_busno+1; 312 printf(" PCIE1 on bus %02x - %02x\n", 313 hose->first_busno,hose->last_busno); 314 315 } else { 316 printf (" PCIE1: disabled\n"); 317 } 318 319 } 320 #else 321 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 322 #endif 323 324 #ifdef CONFIG_PCIE2 325 { 326 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 327 struct pci_controller *hose = &pcie2_hose; 328 int pcie_ep = (host_agent == 3); 329 int pcie_configured = (io_sel == 5 || io_sel == 7); 330 struct pci_region *r = hose->regions; 331 332 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 333 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 334 pcie_ep ? "End Point" : "Root Complex", 335 (uint)pci); 336 if (pci->pme_msg_det) { 337 pci->pme_msg_det = 0xffffffff; 338 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 339 } 340 printf ("\n"); 341 342 /* outbound memory */ 343 pci_set_region(r++, 344 CONFIG_SYS_PCIE2_MEM_BUS, 345 CONFIG_SYS_PCIE2_MEM_PHYS, 346 CONFIG_SYS_PCIE2_MEM_SIZE, 347 PCI_REGION_MEM); 348 349 /* outbound io */ 350 pci_set_region(r++, 351 CONFIG_SYS_PCIE2_IO_BUS, 352 CONFIG_SYS_PCIE2_IO_PHYS, 353 CONFIG_SYS_PCIE2_IO_SIZE, 354 PCI_REGION_IO); 355 356 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 357 /* outbound memory */ 358 pci_set_region(r++, 359 CONFIG_SYS_PCIE2_MEM_BUS2, 360 CONFIG_SYS_PCIE2_MEM_PHYS2, 361 CONFIG_SYS_PCIE2_MEM_SIZE2, 362 PCI_REGION_MEM); 363 #endif 364 hose->region_count = r - hose->regions; 365 hose->first_busno=first_free_busno; 366 367 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 368 first_free_busno=hose->last_busno+1; 369 printf (" PCIE2 on bus %02x - %02x\n", 370 hose->first_busno,hose->last_busno); 371 372 } else { 373 printf (" PCIE2: disabled\n"); 374 } 375 376 } 377 #else 378 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 379 #endif 380 381 382 #ifdef CONFIG_PCI1 383 { 384 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 385 struct pci_controller *hose = &pci1_hose; 386 struct pci_region *r = hose->regions; 387 388 uint pci_agent = (host_agent == 6); 389 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 390 uint pci_32 = 1; 391 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 392 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 393 394 395 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 396 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 397 (pci_32) ? 32 : 64, 398 (pci_speed == 33333000) ? "33" : 399 (pci_speed == 66666000) ? "66" : "unknown", 400 pci_clk_sel ? "sync" : "async", 401 pci_agent ? "agent" : "host", 402 pci_arb ? "arbiter" : "external-arbiter", 403 (uint)pci 404 ); 405 406 /* outbound memory */ 407 pci_set_region(r++, 408 CONFIG_SYS_PCI1_MEM_BUS, 409 CONFIG_SYS_PCI1_MEM_PHYS, 410 CONFIG_SYS_PCI1_MEM_SIZE, 411 PCI_REGION_MEM); 412 413 /* outbound io */ 414 pci_set_region(r++, 415 CONFIG_SYS_PCI1_IO_BUS, 416 CONFIG_SYS_PCI1_IO_PHYS, 417 CONFIG_SYS_PCI1_IO_SIZE, 418 PCI_REGION_IO); 419 420 #ifdef CONFIG_SYS_PCI1_MEM_BUS2 421 /* outbound memory */ 422 pci_set_region(r++, 423 CONFIG_SYS_PCI1_MEM_BUS2, 424 CONFIG_SYS_PCI1_MEM_PHYS2, 425 CONFIG_SYS_PCI1_MEM_SIZE2, 426 PCI_REGION_MEM); 427 #endif 428 hose->region_count = r - hose->regions; 429 hose->first_busno=first_free_busno; 430 431 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 432 first_free_busno=hose->last_busno+1; 433 printf ("PCI on bus %02x - %02x\n", 434 hose->first_busno,hose->last_busno); 435 } else { 436 printf (" PCI: disabled\n"); 437 } 438 } 439 #else 440 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 441 #endif 442 } 443 444 445 int board_early_init_r(void) 446 { 447 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 448 const u8 flash_esel = 1; 449 450 /* 451 * Remap Boot flash + PROMJET region to caching-inhibited 452 * so that flash can be erased properly. 453 */ 454 455 /* Flush d-cache and invalidate i-cache of any FLASH data */ 456 flush_dcache(); 457 invalidate_icache(); 458 459 /* invalidate existing TLB entry for flash + promjet */ 460 disable_tlb(flash_esel); 461 462 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 463 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 464 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 465 466 return 0; 467 } 468 469 #ifdef CONFIG_GET_CLK_FROM_ICS307 470 /* decode S[0-2] to Output Divider (OD) */ 471 static unsigned char 472 ics307_S_to_OD[] = { 473 10, 2, 8, 4, 5, 7, 3, 6 474 }; 475 476 /* Calculate frequency being generated by ICS307-02 clock chip based upon 477 * the control bytes being programmed into it. */ 478 /* XXX: This function should probably go into a common library */ 479 static unsigned long 480 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 481 { 482 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 483 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 484 unsigned long RDW = cw2 & 0x7F; 485 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 486 unsigned long freq; 487 488 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 489 490 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 491 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 492 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 493 * 494 * R6:R0 = Reference Divider Word (RDW) 495 * V8:V0 = VCO Divider Word (VDW) 496 * S2:S0 = Output Divider Select (OD) 497 * F1:F0 = Function of CLK2 Output 498 * TTL = duty cycle 499 * C1:C0 = internal load capacitance for cyrstal 500 */ 501 502 /* Adding 1 to get a "nicely" rounded number, but this needs 503 * more tweaking to get a "properly" rounded number. */ 504 505 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 506 507 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 508 freq); 509 return freq; 510 } 511 512 unsigned long 513 get_board_sys_clk(ulong dummy) 514 { 515 u8 *pixis_base = (u8 *)PIXIS_BASE; 516 517 return ics307_clk_freq ( 518 in_8(pixis_base + PIXIS_VSYSCLK0), 519 in_8(pixis_base + PIXIS_VSYSCLK1), 520 in_8(pixis_base + PIXIS_VSYSCLK2) 521 ); 522 } 523 524 unsigned long 525 get_board_ddr_clk(ulong dummy) 526 { 527 u8 *pixis_base = (u8 *)PIXIS_BASE; 528 529 return ics307_clk_freq ( 530 in_8(pixis_base + PIXIS_VDDRCLK0), 531 in_8(pixis_base + PIXIS_VDDRCLK1), 532 in_8(pixis_base + PIXIS_VDDRCLK2) 533 ); 534 } 535 #else 536 unsigned long 537 get_board_sys_clk(ulong dummy) 538 { 539 u8 i; 540 ulong val = 0; 541 u8 *pixis_base = (u8 *)PIXIS_BASE; 542 543 i = in_8(pixis_base + PIXIS_SPD); 544 i &= 0x07; 545 546 switch (i) { 547 case 0: 548 val = 33333333; 549 break; 550 case 1: 551 val = 40000000; 552 break; 553 case 2: 554 val = 50000000; 555 break; 556 case 3: 557 val = 66666666; 558 break; 559 case 4: 560 val = 83333333; 561 break; 562 case 5: 563 val = 100000000; 564 break; 565 case 6: 566 val = 133333333; 567 break; 568 case 7: 569 val = 166666666; 570 break; 571 } 572 573 return val; 574 } 575 576 unsigned long 577 get_board_ddr_clk(ulong dummy) 578 { 579 u8 i; 580 ulong val = 0; 581 u8 *pixis_base = (u8 *)PIXIS_BASE; 582 583 i = in_8(pixis_base + PIXIS_SPD); 584 i &= 0x38; 585 i >>= 3; 586 587 switch (i) { 588 case 0: 589 val = 33333333; 590 break; 591 case 1: 592 val = 40000000; 593 break; 594 case 2: 595 val = 50000000; 596 break; 597 case 3: 598 val = 66666666; 599 break; 600 case 4: 601 val = 83333333; 602 break; 603 case 5: 604 val = 100000000; 605 break; 606 case 6: 607 val = 133333333; 608 break; 609 case 7: 610 val = 166666666; 611 break; 612 } 613 return val; 614 } 615 #endif 616 617 int sata_initialize(void) 618 { 619 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 620 uint sdrs2_io_sel = 621 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 622 if (sdrs2_io_sel & 0x04) 623 return 1; 624 625 return __sata_initialize(); 626 } 627 628 int board_eth_init(bd_t *bis) 629 { 630 #ifdef CONFIG_TSEC_ENET 631 struct tsec_info_struct tsec_info[2]; 632 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 633 int num = 0; 634 uint sdrs2_io_sel = 635 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 636 637 #ifdef CONFIG_TSEC1 638 SET_STD_TSEC_INFO(tsec_info[num], 1); 639 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 640 tsec_info[num].phyaddr = 0; 641 tsec_info[num].flags |= TSEC_SGMII; 642 } 643 num++; 644 #endif 645 #ifdef CONFIG_TSEC3 646 SET_STD_TSEC_INFO(tsec_info[num], 3); 647 if (sdrs2_io_sel == 4) { 648 tsec_info[num].phyaddr = 1; 649 tsec_info[num].flags |= TSEC_SGMII; 650 } 651 num++; 652 #endif 653 654 if (!num) { 655 printf("No TSECs initialized\n"); 656 return 0; 657 } 658 659 #ifdef CONFIG_FSL_SGMII_RISER 660 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 661 fsl_sgmii_riser_init(tsec_info, num); 662 #endif 663 664 tsec_eth_init(bis, tsec_info, num); 665 #endif 666 return pci_eth_init(bis); 667 } 668 669 #if defined(CONFIG_OF_BOARD_SETUP) 670 void ft_board_setup(void *blob, bd_t *bd) 671 { 672 ft_cpu_setup(blob, bd); 673 674 #ifdef CONFIG_PCI1 675 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 676 #endif 677 #ifdef CONFIG_PCIE2 678 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 679 #endif 680 #ifdef CONFIG_PCIE2 681 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 682 #endif 683 #ifdef CONFIG_PCIE1 684 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); 685 #endif 686 #ifdef CONFIG_FSL_SGMII_RISER 687 fsl_sgmii_riser_fdt_fixup(blob); 688 #endif 689 } 690 #endif 691