1 /* 2 * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <asm/fsl_serdes.h> 34 #include <spd.h> 35 #include <miiphy.h> 36 #include <libfdt.h> 37 #include <spd_sdram.h> 38 #include <fdt_support.h> 39 #include <fsl_mdio.h> 40 #include <tsec.h> 41 #include <netdev.h> 42 #include <sata.h> 43 44 #include "../common/sgmii_riser.h" 45 46 int board_early_init_f (void) 47 { 48 #ifdef CONFIG_MMC 49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 50 51 setbits_be32(&gur->pmuxcr, 52 (MPC85xx_PMUXCR_SDHC_CD | 53 MPC85xx_PMUXCR_SDHC_WP)); 54 #endif 55 return 0; 56 } 57 58 int checkboard (void) 59 { 60 u8 vboot; 61 u8 *pixis_base = (u8 *)PIXIS_BASE; 62 63 puts("Board: MPC8536DS "); 64 #ifdef CONFIG_PHYS_64BIT 65 puts("(36-bit addrmap) "); 66 #endif 67 68 printf ("Sys ID: 0x%02x, " 69 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 70 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 71 in_8(pixis_base + PIXIS_PVER)); 72 73 vboot = in_8(pixis_base + PIXIS_VBOOT); 74 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 75 case PIXIS_VBOOT_LBMAP_NOR0: 76 puts ("vBank: 0\n"); 77 break; 78 case PIXIS_VBOOT_LBMAP_NOR1: 79 puts ("vBank: 1\n"); 80 break; 81 case PIXIS_VBOOT_LBMAP_NOR2: 82 puts ("vBank: 2\n"); 83 break; 84 case PIXIS_VBOOT_LBMAP_NOR3: 85 puts ("vBank: 3\n"); 86 break; 87 case PIXIS_VBOOT_LBMAP_PJET: 88 puts ("Promjet\n"); 89 break; 90 case PIXIS_VBOOT_LBMAP_NAND: 91 puts ("NAND\n"); 92 break; 93 } 94 95 return 0; 96 } 97 98 #if !defined(CONFIG_SPD_EEPROM) 99 /* 100 * Fixed sdram init -- doesn't use serial presence detect. 101 */ 102 103 phys_size_t fixed_sdram (void) 104 { 105 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 106 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 107 uint d_init; 108 109 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 110 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 111 112 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 113 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 114 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 115 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 116 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 117 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 118 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 119 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 120 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 121 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 122 123 #if defined (CONFIG_DDR_ECC) 124 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 125 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 126 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 127 #endif 128 asm("sync;isync"); 129 130 udelay(500); 131 132 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 133 134 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 135 d_init = 1; 136 debug("DDR - 1st controller: memory initializing\n"); 137 /* 138 * Poll until memory is initialized. 139 * 512 Meg at 400 might hit this 200 times or so. 140 */ 141 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 142 udelay(1000); 143 } 144 debug("DDR: memory initialized\n\n"); 145 asm("sync; isync"); 146 udelay(500); 147 #endif 148 149 return 512 * 1024 * 1024; 150 } 151 152 #endif 153 154 #ifdef CONFIG_PCI1 155 static struct pci_controller pci1_hose; 156 #endif 157 158 #ifdef CONFIG_PCI 159 void pci_init_board(void) 160 { 161 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 162 struct fsl_pci_info pci_info; 163 u32 devdisr, pordevsr; 164 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 165 int first_free_busno; 166 167 first_free_busno = fsl_pcie_init_board(0); 168 169 #ifdef CONFIG_PCI1 170 devdisr = in_be32(&gur->devdisr); 171 pordevsr = in_be32(&gur->pordevsr); 172 porpllsr = in_be32(&gur->porpllsr); 173 174 pci_speed = 66666000; 175 pci_32 = 1; 176 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 177 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 178 179 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 180 SET_STD_PCI_INFO(pci_info, 1); 181 set_next_law(pci_info.mem_phys, 182 law_size_bits(pci_info.mem_size), pci_info.law); 183 set_next_law(pci_info.io_phys, 184 law_size_bits(pci_info.io_size), pci_info.law); 185 186 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); 187 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 188 (pci_32) ? 32 : 64, 189 (pci_speed == 33333000) ? "33" : 190 (pci_speed == 66666000) ? "66" : "unknown", 191 pci_clk_sel ? "sync" : "async", 192 pci_agent ? "agent" : "host", 193 pci_arb ? "arbiter" : "external-arbiter", 194 pci_info.regs); 195 196 first_free_busno = fsl_pci_init_port(&pci_info, 197 &pci1_hose, first_free_busno); 198 } else { 199 printf("PCI: disabled\n"); 200 } 201 202 puts("\n"); 203 #else 204 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 205 #endif 206 } 207 #endif 208 209 int board_early_init_r(void) 210 { 211 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 212 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 213 214 /* 215 * Remap Boot flash + PROMJET region to caching-inhibited 216 * so that flash can be erased properly. 217 */ 218 219 /* Flush d-cache and invalidate i-cache of any FLASH data */ 220 flush_dcache(); 221 invalidate_icache(); 222 223 /* invalidate existing TLB entry for flash + promjet */ 224 disable_tlb(flash_esel); 225 226 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 227 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 228 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 229 230 return 0; 231 } 232 233 int board_eth_init(bd_t *bis) 234 { 235 #ifdef CONFIG_TSEC_ENET 236 struct fsl_pq_mdio_info mdio_info; 237 struct tsec_info_struct tsec_info[2]; 238 int num = 0; 239 240 #ifdef CONFIG_TSEC1 241 SET_STD_TSEC_INFO(tsec_info[num], 1); 242 if (is_serdes_configured(SGMII_TSEC1)) { 243 puts("eTSEC1 is in sgmii mode.\n"); 244 tsec_info[num].phyaddr = 0; 245 tsec_info[num].flags |= TSEC_SGMII; 246 } 247 num++; 248 #endif 249 #ifdef CONFIG_TSEC3 250 SET_STD_TSEC_INFO(tsec_info[num], 3); 251 if (is_serdes_configured(SGMII_TSEC3)) { 252 puts("eTSEC3 is in sgmii mode.\n"); 253 tsec_info[num].phyaddr = 1; 254 tsec_info[num].flags |= TSEC_SGMII; 255 } 256 num++; 257 #endif 258 259 if (!num) { 260 printf("No TSECs initialized\n"); 261 return 0; 262 } 263 264 #ifdef CONFIG_FSL_SGMII_RISER 265 if (is_serdes_configured(SGMII_TSEC1) || 266 is_serdes_configured(SGMII_TSEC3)) { 267 fsl_sgmii_riser_init(tsec_info, num); 268 } 269 #endif 270 271 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 272 mdio_info.name = DEFAULT_MII_NAME; 273 fsl_pq_mdio_init(bis, &mdio_info); 274 275 tsec_eth_init(bis, tsec_info, num); 276 #endif 277 return pci_eth_init(bis); 278 } 279 280 #if defined(CONFIG_OF_BOARD_SETUP) 281 void ft_board_setup(void *blob, bd_t *bd) 282 { 283 ft_cpu_setup(blob, bd); 284 285 FT_FSL_PCI_SETUP; 286 287 #ifdef CONFIG_FSL_SGMII_RISER 288 fsl_sgmii_riser_fdt_fixup(blob); 289 #endif 290 } 291 #endif 292