1 /* 2 * Copyright 2008 Freescale Semiconductor. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <spd.h> 34 #include <miiphy.h> 35 #include <libfdt.h> 36 #include <spd_sdram.h> 37 #include <fdt_support.h> 38 #include <tsec.h> 39 #include <netdev.h> 40 #include <sata.h> 41 42 #include "../common/pixis.h" 43 #include "../common/sgmii_riser.h" 44 45 phys_size_t fixed_sdram(void); 46 47 int board_early_init_f (void) 48 { 49 #ifdef CONFIG_MMC 50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 51 52 setbits_be32(&gur->pmuxcr, 53 (MPC85xx_PMUXCR_SD_DATA | 54 MPC85xx_PMUXCR_SDHC_CD | 55 MPC85xx_PMUXCR_SDHC_WP)); 56 57 #endif 58 return 0; 59 } 60 61 int checkboard (void) 62 { 63 u8 vboot; 64 u8 *pixis_base = (u8 *)PIXIS_BASE; 65 66 puts("Board: MPC8536DS "); 67 #ifdef CONFIG_PHYS_64BIT 68 puts("(36-bit addrmap) "); 69 #endif 70 71 printf ("Sys ID: 0x%02x, " 72 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 73 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 74 in_8(pixis_base + PIXIS_PVER)); 75 76 vboot = in_8(pixis_base + PIXIS_VBOOT); 77 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 78 case PIXIS_VBOOT_LBMAP_NOR0: 79 puts ("vBank: 0\n"); 80 break; 81 case PIXIS_VBOOT_LBMAP_NOR1: 82 puts ("vBank: 1\n"); 83 break; 84 case PIXIS_VBOOT_LBMAP_NOR2: 85 puts ("vBank: 2\n"); 86 break; 87 case PIXIS_VBOOT_LBMAP_NOR3: 88 puts ("vBank: 3\n"); 89 break; 90 case PIXIS_VBOOT_LBMAP_PJET: 91 puts ("Promjet\n"); 92 break; 93 case PIXIS_VBOOT_LBMAP_NAND: 94 puts ("NAND\n"); 95 break; 96 } 97 98 return 0; 99 } 100 101 phys_size_t 102 initdram(int board_type) 103 { 104 phys_size_t dram_size = 0; 105 106 puts("Initializing...."); 107 108 #ifdef CONFIG_SPD_EEPROM 109 dram_size = fsl_ddr_sdram(); 110 #else 111 dram_size = fixed_sdram(); 112 #endif 113 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 114 dram_size *= 0x100000; 115 116 puts(" DDR: "); 117 return dram_size; 118 } 119 120 #if !defined(CONFIG_SPD_EEPROM) 121 /* 122 * Fixed sdram init -- doesn't use serial presence detect. 123 */ 124 125 phys_size_t fixed_sdram (void) 126 { 127 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 128 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 129 uint d_init; 130 131 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 132 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 133 134 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 135 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 136 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 137 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 138 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 139 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 140 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 141 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 142 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 143 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 144 145 #if defined (CONFIG_DDR_ECC) 146 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 147 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 148 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 149 #endif 150 asm("sync;isync"); 151 152 udelay(500); 153 154 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 155 156 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 157 d_init = 1; 158 debug("DDR - 1st controller: memory initializing\n"); 159 /* 160 * Poll until memory is initialized. 161 * 512 Meg at 400 might hit this 200 times or so. 162 */ 163 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 164 udelay(1000); 165 } 166 debug("DDR: memory initialized\n\n"); 167 asm("sync; isync"); 168 udelay(500); 169 #endif 170 171 return 512 * 1024 * 1024; 172 } 173 174 #endif 175 176 #ifdef CONFIG_PCI1 177 static struct pci_controller pci1_hose; 178 #endif 179 180 #ifdef CONFIG_PCIE1 181 static struct pci_controller pcie1_hose; 182 #endif 183 184 #ifdef CONFIG_PCIE2 185 static struct pci_controller pcie2_hose; 186 #endif 187 188 #ifdef CONFIG_PCIE3 189 static struct pci_controller pcie3_hose; 190 #endif 191 192 int first_free_busno=0; 193 194 void 195 pci_init_board(void) 196 { 197 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 198 uint devdisr = gur->devdisr; 199 uint sdrs2_io_sel = 200 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 201 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 202 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; 203 204 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ 205 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); 206 207 if (sdrs2_io_sel == 7) 208 printf(" Serdes2 disalbed\n"); 209 else if (sdrs2_io_sel == 4) { 210 printf(" eTSEC1 is in sgmii mode.\n"); 211 printf(" eTSEC3 is in sgmii mode.\n"); 212 } else if (sdrs2_io_sel == 6) 213 printf(" eTSEC1 is in sgmii mode.\n"); 214 215 #ifdef CONFIG_PCIE3 216 { 217 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; 218 struct pci_controller *hose = &pcie3_hose; 219 int pcie_ep = (host_agent == 1); 220 int pcie_configured = (io_sel == 7); 221 struct pci_region *r = hose->regions; 222 223 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 224 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", 225 pcie_ep ? "End Point" : "Root Complex", 226 (uint)pci); 227 if (pci->pme_msg_det) { 228 pci->pme_msg_det = 0xffffffff; 229 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 230 } 231 printf ("\n"); 232 233 /* outbound memory */ 234 pci_set_region(r++, 235 CONFIG_SYS_PCIE3_MEM_BUS, 236 CONFIG_SYS_PCIE3_MEM_PHYS, 237 CONFIG_SYS_PCIE3_MEM_SIZE, 238 PCI_REGION_MEM); 239 240 /* outbound io */ 241 pci_set_region(r++, 242 CONFIG_SYS_PCIE3_IO_BUS, 243 CONFIG_SYS_PCIE3_IO_PHYS, 244 CONFIG_SYS_PCIE3_IO_SIZE, 245 PCI_REGION_IO); 246 247 hose->region_count = r - hose->regions; 248 249 hose->first_busno=first_free_busno; 250 251 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 252 253 first_free_busno=hose->last_busno+1; 254 printf (" PCIE3 on bus %02x - %02x\n", 255 hose->first_busno,hose->last_busno); 256 } else { 257 printf (" PCIE3: disabled\n"); 258 } 259 } 260 #else 261 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ 262 #endif 263 264 #ifdef CONFIG_PCIE1 265 { 266 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; 267 struct pci_controller *hose = &pcie1_hose; 268 int pcie_ep = (host_agent == 5); 269 int pcie_configured = (io_sel == 2 || io_sel == 3 270 || io_sel == 5 || io_sel == 7); 271 struct pci_region *r = hose->regions; 272 273 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 274 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", 275 pcie_ep ? "End Point" : "Root Complex", 276 (uint)pci); 277 if (pci->pme_msg_det) { 278 pci->pme_msg_det = 0xffffffff; 279 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 280 } 281 printf ("\n"); 282 283 /* outbound memory */ 284 pci_set_region(r++, 285 CONFIG_SYS_PCIE1_MEM_BUS, 286 CONFIG_SYS_PCIE1_MEM_PHYS, 287 CONFIG_SYS_PCIE1_MEM_SIZE, 288 PCI_REGION_MEM); 289 290 /* outbound io */ 291 pci_set_region(r++, 292 CONFIG_SYS_PCIE1_IO_BUS, 293 CONFIG_SYS_PCIE1_IO_PHYS, 294 CONFIG_SYS_PCIE1_IO_SIZE, 295 PCI_REGION_IO); 296 297 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 298 /* outbound memory */ 299 pci_set_region(r++, 300 CONFIG_SYS_PCIE1_MEM_BUS2, 301 CONFIG_SYS_PCIE1_MEM_PHYS2, 302 CONFIG_SYS_PCIE1_MEM_SIZE2, 303 PCI_REGION_MEM); 304 #endif 305 hose->region_count = r - hose->regions; 306 hose->first_busno=first_free_busno; 307 308 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 309 310 first_free_busno=hose->last_busno+1; 311 printf(" PCIE1 on bus %02x - %02x\n", 312 hose->first_busno,hose->last_busno); 313 314 } else { 315 printf (" PCIE1: disabled\n"); 316 } 317 } 318 #else 319 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ 320 #endif 321 322 #ifdef CONFIG_PCIE2 323 { 324 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; 325 struct pci_controller *hose = &pcie2_hose; 326 int pcie_ep = (host_agent == 3); 327 int pcie_configured = (io_sel == 5 || io_sel == 7); 328 struct pci_region *r = hose->regions; 329 330 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 331 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", 332 pcie_ep ? "End Point" : "Root Complex", 333 (uint)pci); 334 if (pci->pme_msg_det) { 335 pci->pme_msg_det = 0xffffffff; 336 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); 337 } 338 printf ("\n"); 339 340 /* outbound memory */ 341 pci_set_region(r++, 342 CONFIG_SYS_PCIE2_MEM_BUS, 343 CONFIG_SYS_PCIE2_MEM_PHYS, 344 CONFIG_SYS_PCIE2_MEM_SIZE, 345 PCI_REGION_MEM); 346 347 /* outbound io */ 348 pci_set_region(r++, 349 CONFIG_SYS_PCIE2_IO_BUS, 350 CONFIG_SYS_PCIE2_IO_PHYS, 351 CONFIG_SYS_PCIE2_IO_SIZE, 352 PCI_REGION_IO); 353 354 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 355 /* outbound memory */ 356 pci_set_region(r++, 357 CONFIG_SYS_PCIE2_MEM_BUS2, 358 CONFIG_SYS_PCIE2_MEM_PHYS2, 359 CONFIG_SYS_PCIE2_MEM_SIZE2, 360 PCI_REGION_MEM); 361 #endif 362 hose->region_count = r - hose->regions; 363 hose->first_busno=first_free_busno; 364 365 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 366 first_free_busno=hose->last_busno+1; 367 printf (" PCIE2 on bus %02x - %02x\n", 368 hose->first_busno,hose->last_busno); 369 370 } else { 371 printf (" PCIE2: disabled\n"); 372 } 373 } 374 #else 375 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ 376 #endif 377 378 #ifdef CONFIG_PCI1 379 { 380 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; 381 struct pci_controller *hose = &pci1_hose; 382 struct pci_region *r = hose->regions; 383 384 uint pci_agent = (host_agent == 6); 385 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ 386 uint pci_32 = 1; 387 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ 388 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ 389 390 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 391 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", 392 (pci_32) ? 32 : 64, 393 (pci_speed == 33333000) ? "33" : 394 (pci_speed == 66666000) ? "66" : "unknown", 395 pci_clk_sel ? "sync" : "async", 396 pci_agent ? "agent" : "host", 397 pci_arb ? "arbiter" : "external-arbiter", 398 (uint)pci 399 ); 400 401 /* outbound memory */ 402 pci_set_region(r++, 403 CONFIG_SYS_PCI1_MEM_BUS, 404 CONFIG_SYS_PCI1_MEM_PHYS, 405 CONFIG_SYS_PCI1_MEM_SIZE, 406 PCI_REGION_MEM); 407 408 /* outbound io */ 409 pci_set_region(r++, 410 CONFIG_SYS_PCI1_IO_BUS, 411 CONFIG_SYS_PCI1_IO_PHYS, 412 CONFIG_SYS_PCI1_IO_SIZE, 413 PCI_REGION_IO); 414 415 #ifdef CONFIG_SYS_PCI1_MEM_BUS2 416 /* outbound memory */ 417 pci_set_region(r++, 418 CONFIG_SYS_PCI1_MEM_BUS2, 419 CONFIG_SYS_PCI1_MEM_PHYS2, 420 CONFIG_SYS_PCI1_MEM_SIZE2, 421 PCI_REGION_MEM); 422 #endif 423 hose->region_count = r - hose->regions; 424 hose->first_busno=first_free_busno; 425 426 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); 427 first_free_busno=hose->last_busno+1; 428 printf ("PCI on bus %02x - %02x\n", 429 hose->first_busno,hose->last_busno); 430 } else { 431 printf (" PCI: disabled\n"); 432 } 433 } 434 #else 435 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ 436 #endif 437 } 438 439 int board_early_init_r(void) 440 { 441 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 442 const u8 flash_esel = 1; 443 444 /* 445 * Remap Boot flash + PROMJET region to caching-inhibited 446 * so that flash can be erased properly. 447 */ 448 449 /* Flush d-cache and invalidate i-cache of any FLASH data */ 450 flush_dcache(); 451 invalidate_icache(); 452 453 /* invalidate existing TLB entry for flash + promjet */ 454 disable_tlb(flash_esel); 455 456 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 457 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 458 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 459 460 return 0; 461 } 462 463 #ifdef CONFIG_GET_CLK_FROM_ICS307 464 /* decode S[0-2] to Output Divider (OD) */ 465 static unsigned char 466 ics307_S_to_OD[] = { 467 10, 2, 8, 4, 5, 7, 3, 6 468 }; 469 470 /* Calculate frequency being generated by ICS307-02 clock chip based upon 471 * the control bytes being programmed into it. */ 472 /* XXX: This function should probably go into a common library */ 473 static unsigned long 474 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) 475 { 476 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; 477 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); 478 unsigned long RDW = cw2 & 0x7F; 479 unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; 480 unsigned long freq; 481 482 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ 483 484 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 485 * cw1: V8 V7 V6 V5 V4 V3 V2 V1 486 * cw2: V0 R6 R5 R4 R3 R2 R1 R0 487 * 488 * R6:R0 = Reference Divider Word (RDW) 489 * V8:V0 = VCO Divider Word (VDW) 490 * S2:S0 = Output Divider Select (OD) 491 * F1:F0 = Function of CLK2 Output 492 * TTL = duty cycle 493 * C1:C0 = internal load capacitance for cyrstal 494 */ 495 496 /* Adding 1 to get a "nicely" rounded number, but this needs 497 * more tweaking to get a "properly" rounded number. */ 498 499 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); 500 501 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, 502 freq); 503 return freq; 504 } 505 506 unsigned long 507 get_board_sys_clk(ulong dummy) 508 { 509 u8 *pixis_base = (u8 *)PIXIS_BASE; 510 511 return ics307_clk_freq ( 512 in_8(pixis_base + PIXIS_VSYSCLK0), 513 in_8(pixis_base + PIXIS_VSYSCLK1), 514 in_8(pixis_base + PIXIS_VSYSCLK2) 515 ); 516 } 517 518 unsigned long 519 get_board_ddr_clk(ulong dummy) 520 { 521 u8 *pixis_base = (u8 *)PIXIS_BASE; 522 523 return ics307_clk_freq ( 524 in_8(pixis_base + PIXIS_VDDRCLK0), 525 in_8(pixis_base + PIXIS_VDDRCLK1), 526 in_8(pixis_base + PIXIS_VDDRCLK2) 527 ); 528 } 529 #else 530 unsigned long 531 get_board_sys_clk(ulong dummy) 532 { 533 u8 i; 534 ulong val = 0; 535 u8 *pixis_base = (u8 *)PIXIS_BASE; 536 537 i = in_8(pixis_base + PIXIS_SPD); 538 i &= 0x07; 539 540 switch (i) { 541 case 0: 542 val = 33333333; 543 break; 544 case 1: 545 val = 40000000; 546 break; 547 case 2: 548 val = 50000000; 549 break; 550 case 3: 551 val = 66666666; 552 break; 553 case 4: 554 val = 83333333; 555 break; 556 case 5: 557 val = 100000000; 558 break; 559 case 6: 560 val = 133333333; 561 break; 562 case 7: 563 val = 166666666; 564 break; 565 } 566 567 return val; 568 } 569 570 unsigned long 571 get_board_ddr_clk(ulong dummy) 572 { 573 u8 i; 574 ulong val = 0; 575 u8 *pixis_base = (u8 *)PIXIS_BASE; 576 577 i = in_8(pixis_base + PIXIS_SPD); 578 i &= 0x38; 579 i >>= 3; 580 581 switch (i) { 582 case 0: 583 val = 33333333; 584 break; 585 case 1: 586 val = 40000000; 587 break; 588 case 2: 589 val = 50000000; 590 break; 591 case 3: 592 val = 66666666; 593 break; 594 case 4: 595 val = 83333333; 596 break; 597 case 5: 598 val = 100000000; 599 break; 600 case 6: 601 val = 133333333; 602 break; 603 case 7: 604 val = 166666666; 605 break; 606 } 607 return val; 608 } 609 #endif 610 611 int sata_initialize(void) 612 { 613 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 614 uint sdrs2_io_sel = 615 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 616 if (sdrs2_io_sel & 0x04) 617 return 1; 618 619 return __sata_initialize(); 620 } 621 622 int board_eth_init(bd_t *bis) 623 { 624 #ifdef CONFIG_TSEC_ENET 625 struct tsec_info_struct tsec_info[2]; 626 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 627 int num = 0; 628 uint sdrs2_io_sel = 629 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; 630 631 #ifdef CONFIG_TSEC1 632 SET_STD_TSEC_INFO(tsec_info[num], 1); 633 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { 634 tsec_info[num].phyaddr = 0; 635 tsec_info[num].flags |= TSEC_SGMII; 636 } 637 num++; 638 #endif 639 #ifdef CONFIG_TSEC3 640 SET_STD_TSEC_INFO(tsec_info[num], 3); 641 if (sdrs2_io_sel == 4) { 642 tsec_info[num].phyaddr = 1; 643 tsec_info[num].flags |= TSEC_SGMII; 644 } 645 num++; 646 #endif 647 648 if (!num) { 649 printf("No TSECs initialized\n"); 650 return 0; 651 } 652 653 #ifdef CONFIG_FSL_SGMII_RISER 654 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) 655 fsl_sgmii_riser_init(tsec_info, num); 656 #endif 657 658 tsec_eth_init(bis, tsec_info, num); 659 #endif 660 return pci_eth_init(bis); 661 } 662 663 #if defined(CONFIG_OF_BOARD_SETUP) 664 void ft_board_setup(void *blob, bd_t *bd) 665 { 666 ft_cpu_setup(blob, bd); 667 668 #ifdef CONFIG_PCI1 669 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); 670 #endif 671 #ifdef CONFIG_PCIE2 672 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); 673 #endif 674 #ifdef CONFIG_PCIE2 675 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); 676 #endif 677 #ifdef CONFIG_PCIE1 678 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); 679 #endif 680 #ifdef CONFIG_FSL_SGMII_RISER 681 fsl_sgmii_riser_fdt_fixup(blob); 682 #endif 683 } 684 #endif 685