1 /* 2 * Copyright 2008-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <pci.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_pci.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/io.h> 33 #include <asm/fsl_serdes.h> 34 #include <spd.h> 35 #include <miiphy.h> 36 #include <libfdt.h> 37 #include <spd_sdram.h> 38 #include <fdt_support.h> 39 #include <tsec.h> 40 #include <netdev.h> 41 #include <sata.h> 42 43 #include "../common/sgmii_riser.h" 44 45 phys_size_t fixed_sdram(void); 46 47 int board_early_init_f (void) 48 { 49 #ifdef CONFIG_MMC 50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 51 52 setbits_be32(&gur->pmuxcr, 53 (MPC85xx_PMUXCR_SD_DATA | 54 MPC85xx_PMUXCR_SDHC_CD | 55 MPC85xx_PMUXCR_SDHC_WP)); 56 57 #endif 58 return 0; 59 } 60 61 int checkboard (void) 62 { 63 u8 vboot; 64 u8 *pixis_base = (u8 *)PIXIS_BASE; 65 66 puts("Board: MPC8536DS "); 67 #ifdef CONFIG_PHYS_64BIT 68 puts("(36-bit addrmap) "); 69 #endif 70 71 printf ("Sys ID: 0x%02x, " 72 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", 73 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), 74 in_8(pixis_base + PIXIS_PVER)); 75 76 vboot = in_8(pixis_base + PIXIS_VBOOT); 77 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { 78 case PIXIS_VBOOT_LBMAP_NOR0: 79 puts ("vBank: 0\n"); 80 break; 81 case PIXIS_VBOOT_LBMAP_NOR1: 82 puts ("vBank: 1\n"); 83 break; 84 case PIXIS_VBOOT_LBMAP_NOR2: 85 puts ("vBank: 2\n"); 86 break; 87 case PIXIS_VBOOT_LBMAP_NOR3: 88 puts ("vBank: 3\n"); 89 break; 90 case PIXIS_VBOOT_LBMAP_PJET: 91 puts ("Promjet\n"); 92 break; 93 case PIXIS_VBOOT_LBMAP_NAND: 94 puts ("NAND\n"); 95 break; 96 } 97 98 return 0; 99 } 100 101 phys_size_t 102 initdram(int board_type) 103 { 104 phys_size_t dram_size = 0; 105 106 puts("Initializing...."); 107 108 #ifdef CONFIG_SPD_EEPROM 109 dram_size = fsl_ddr_sdram(); 110 #else 111 dram_size = fixed_sdram(); 112 #endif 113 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 114 dram_size *= 0x100000; 115 116 puts(" DDR: "); 117 return dram_size; 118 } 119 120 #if !defined(CONFIG_SPD_EEPROM) 121 /* 122 * Fixed sdram init -- doesn't use serial presence detect. 123 */ 124 125 phys_size_t fixed_sdram (void) 126 { 127 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; 128 volatile ccsr_ddr_t *ddr= &immap->im_ddr; 129 uint d_init; 130 131 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 132 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 133 134 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 135 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 136 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 137 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 138 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; 139 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; 140 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 141 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; 142 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; 143 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; 144 145 #if defined (CONFIG_DDR_ECC) 146 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; 147 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; 148 ddr->err_sbe = CONFIG_SYS_DDR_SBE; 149 #endif 150 asm("sync;isync"); 151 152 udelay(500); 153 154 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; 155 156 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 157 d_init = 1; 158 debug("DDR - 1st controller: memory initializing\n"); 159 /* 160 * Poll until memory is initialized. 161 * 512 Meg at 400 might hit this 200 times or so. 162 */ 163 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { 164 udelay(1000); 165 } 166 debug("DDR: memory initialized\n\n"); 167 asm("sync; isync"); 168 udelay(500); 169 #endif 170 171 return 512 * 1024 * 1024; 172 } 173 174 #endif 175 176 #ifdef CONFIG_PCI1 177 static struct pci_controller pci1_hose; 178 #endif 179 180 #ifdef CONFIG_PCIE1 181 static struct pci_controller pcie1_hose; 182 #endif 183 184 #ifdef CONFIG_PCIE2 185 static struct pci_controller pcie2_hose; 186 #endif 187 188 #ifdef CONFIG_PCIE3 189 static struct pci_controller pcie3_hose; 190 #endif 191 192 #ifdef CONFIG_PCI 193 void pci_init_board(void) 194 { 195 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 196 struct fsl_pci_info pci_info[4]; 197 u32 devdisr, pordevsr, io_sel; 198 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; 199 int first_free_busno = 0; 200 int num = 0; 201 202 int pcie_ep, pcie_configured; 203 204 devdisr = in_be32(&gur->devdisr); 205 pordevsr = in_be32(&gur->pordevsr); 206 porpllsr = in_be32(&gur->porpllsr); 207 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; 208 209 debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); 210 211 puts("\n"); 212 #ifdef CONFIG_PCIE3 213 pcie_configured = is_serdes_configured(PCIE3); 214 215 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ 216 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, 217 LAW_TRGT_IF_PCIE_3); 218 set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, 219 LAW_TRGT_IF_PCIE_3); 220 SET_STD_PCIE_INFO(pci_info[num], 3); 221 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); 222 printf("PCIE3: connected to Slot3 as %s (base address %lx)\n", 223 pcie_ep ? "Endpoint" : "Root Complex", 224 pci_info[num].regs); 225 first_free_busno = fsl_pci_init_port(&pci_info[num++], 226 &pcie3_hose, first_free_busno); 227 } else { 228 printf("PCIE3: disabled\n"); 229 } 230 231 puts("\n"); 232 #else 233 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ 234 #endif 235 236 #ifdef CONFIG_PCIE1 237 pcie_configured = is_serdes_configured(PCIE1); 238 239 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ 240 set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, 241 LAW_TRGT_IF_PCIE_1); 242 set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, 243 LAW_TRGT_IF_PCIE_1); 244 SET_STD_PCIE_INFO(pci_info[num], 1); 245 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); 246 printf("PCIE1: connected to Slot1 as %s (base address %lx)\n", 247 pcie_ep ? "Endpoint" : "Root Complex", 248 pci_info[num].regs); 249 first_free_busno = fsl_pci_init_port(&pci_info[num++], 250 &pcie1_hose, first_free_busno); 251 } else { 252 printf("PCIE1: disabled\n"); 253 } 254 255 puts("\n"); 256 #else 257 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ 258 #endif 259 260 #ifdef CONFIG_PCIE2 261 pcie_configured = is_serdes_configured(PCIE2); 262 263 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ 264 set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, 265 LAW_TRGT_IF_PCIE_2); 266 set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, 267 LAW_TRGT_IF_PCIE_2); 268 SET_STD_PCIE_INFO(pci_info[num], 2); 269 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); 270 printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n", 271 pcie_ep ? "Endpoint" : "Root Complex", 272 pci_info[num].regs); 273 first_free_busno = fsl_pci_init_port(&pci_info[num++], 274 &pcie2_hose, first_free_busno); 275 } else { 276 printf("PCIE2: disabled\n"); 277 } 278 279 puts("\n"); 280 #else 281 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ 282 #endif 283 284 #ifdef CONFIG_PCI1 285 pci_speed = 66666000; 286 pci_32 = 1; 287 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; 288 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; 289 290 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { 291 set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, 292 LAW_TRGT_IF_PCI); 293 set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, 294 LAW_TRGT_IF_PCI); 295 SET_STD_PCI_INFO(pci_info[num], 1); 296 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); 297 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", 298 (pci_32) ? 32 : 64, 299 (pci_speed == 33333000) ? "33" : 300 (pci_speed == 66666000) ? "66" : "unknown", 301 pci_clk_sel ? "sync" : "async", 302 pci_agent ? "agent" : "host", 303 pci_arb ? "arbiter" : "external-arbiter", 304 pci_info[num].regs); 305 306 first_free_busno = fsl_pci_init_port(&pci_info[num++], 307 &pci1_hose, first_free_busno); 308 } else { 309 printf("PCI: disabled\n"); 310 } 311 312 puts("\n"); 313 #else 314 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ 315 #endif 316 } 317 #endif 318 319 int board_early_init_r(void) 320 { 321 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 322 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 323 324 /* 325 * Remap Boot flash + PROMJET region to caching-inhibited 326 * so that flash can be erased properly. 327 */ 328 329 /* Flush d-cache and invalidate i-cache of any FLASH data */ 330 flush_dcache(); 331 invalidate_icache(); 332 333 /* invalidate existing TLB entry for flash + promjet */ 334 disable_tlb(flash_esel); 335 336 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ 337 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 338 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ 339 340 return 0; 341 } 342 343 int board_eth_init(bd_t *bis) 344 { 345 #ifdef CONFIG_TSEC_ENET 346 struct tsec_info_struct tsec_info[2]; 347 int num = 0; 348 349 #ifdef CONFIG_TSEC1 350 SET_STD_TSEC_INFO(tsec_info[num], 1); 351 if (is_serdes_configured(SGMII_TSEC1)) { 352 puts("eTSEC1 is in sgmii mode.\n"); 353 tsec_info[num].phyaddr = 0; 354 tsec_info[num].flags |= TSEC_SGMII; 355 } 356 num++; 357 #endif 358 #ifdef CONFIG_TSEC3 359 SET_STD_TSEC_INFO(tsec_info[num], 3); 360 if (is_serdes_configured(SGMII_TSEC3)) { 361 puts("eTSEC3 is in sgmii mode.\n"); 362 tsec_info[num].phyaddr = 1; 363 tsec_info[num].flags |= TSEC_SGMII; 364 } 365 num++; 366 #endif 367 368 if (!num) { 369 printf("No TSECs initialized\n"); 370 return 0; 371 } 372 373 #ifdef CONFIG_FSL_SGMII_RISER 374 if (is_serdes_configured(SGMII_TSEC1) || 375 is_serdes_configured(SGMII_TSEC3)) { 376 fsl_sgmii_riser_init(tsec_info, num); 377 } 378 #endif 379 380 tsec_eth_init(bis, tsec_info, num); 381 #endif 382 return pci_eth_init(bis); 383 } 384 385 #if defined(CONFIG_OF_BOARD_SETUP) 386 void ft_board_setup(void *blob, bd_t *bd) 387 { 388 ft_cpu_setup(blob, bd); 389 390 FT_FSL_PCI_SETUP; 391 392 #ifdef CONFIG_FSL_SGMII_RISER 393 fsl_sgmii_riser_fdt_fixup(blob); 394 #endif 395 } 396 #endif 397