1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15 #include <common.h> 16 #include <i2c.h> 17 #include <asm/io.h> 18 #include <spd_sdram.h> 19 #include <vsc7385.h> 20 21 22 #if defined(CFG_DRAM_TEST) 23 int 24 testdram(void) 25 { 26 uint *pstart = (uint *) CFG_MEMTEST_START; 27 uint *pend = (uint *) CFG_MEMTEST_END; 28 uint *p; 29 30 printf("Testing DRAM from 0x%08x to 0x%08x\n", 31 CFG_MEMTEST_START, 32 CFG_MEMTEST_END); 33 34 printf("DRAM test phase 1:\n"); 35 for (p = pstart; p < pend; p++) 36 *p = 0xaaaaaaaa; 37 38 for (p = pstart; p < pend; p++) { 39 if (*p != 0xaaaaaaaa) { 40 printf("DRAM test fails at: %08x\n", (uint) p); 41 return 1; 42 } 43 } 44 45 printf("DRAM test phase 2:\n"); 46 for (p = pstart; p < pend; p++) 47 *p = 0x55555555; 48 49 for (p = pstart; p < pend; p++) { 50 if (*p != 0x55555555) { 51 printf("DRAM test fails at: %08x\n", (uint) p); 52 return 1; 53 } 54 } 55 56 printf("DRAM test passed.\n"); 57 return 0; 58 } 59 #endif 60 61 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 62 void ddr_enable_ecc(unsigned int dram_size); 63 #endif 64 int fixed_sdram(void); 65 66 long int initdram(int board_type) 67 { 68 immap_t *im = (immap_t *) CFG_IMMR; 69 u32 msize = 0; 70 71 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 72 return -1; 73 74 #if defined(CONFIG_SPD_EEPROM) 75 msize = spd_sdram(); 76 #else 77 msize = fixed_sdram(); 78 #endif 79 80 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 81 /* Initialize DDR ECC byte */ 82 ddr_enable_ecc(msize * 1024 * 1024); 83 #endif 84 /* return total bus DDR size(bytes) */ 85 return (msize * 1024 * 1024); 86 } 87 88 #if !defined(CONFIG_SPD_EEPROM) 89 /************************************************************************* 90 * fixed sdram init -- doesn't use serial presence detect. 91 ************************************************************************/ 92 int fixed_sdram(void) 93 { 94 immap_t *im = (immap_t *) CFG_IMMR; 95 u32 msize = CFG_DDR_SIZE * 1024 * 1024; 96 u32 msize_log2 = __ilog2(msize); 97 98 im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; 99 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 100 101 im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; 102 udelay(50000); 103 104 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; 105 udelay(1000); 106 107 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; 108 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; 109 udelay(1000); 110 111 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 112 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 113 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 114 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 115 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 116 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 117 im->ddr.sdram_mode = CFG_DDR_MODE; 118 im->ddr.sdram_mode2 = CFG_DDR_MODE2; 119 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 120 sync(); 121 udelay(1000); 122 123 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 124 udelay(2000); 125 return CFG_DDR_SIZE; 126 } 127 #endif /*!CFG_SPD_EEPROM */ 128 129 int checkboard(void) 130 { 131 puts("Board: Freescale MPC837xERDB\n"); 132 return 0; 133 } 134 135 /* 136 * Miscellaneous late-boot configurations 137 * 138 * If a VSC7385 microcode image is present, then upload it. 139 */ 140 int misc_init_r(void) 141 { 142 int rc = 0; 143 144 #ifdef CONFIG_VSC7385_IMAGE 145 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, 146 CONFIG_VSC7385_IMAGE_SIZE)) { 147 puts("Failure uploading VSC7385 microcode.\n"); 148 rc = 1; 149 } 150 #endif 151 152 return rc; 153 } 154 155 #if defined(CONFIG_OF_BOARD_SETUP) 156 157 void ft_board_setup(void *blob, bd_t *bd) 158 { 159 #ifdef CONFIG_PCI 160 ft_pci_setup(blob, bd); 161 #endif 162 ft_cpu_setup(blob, bd); 163 } 164 #endif /* CONFIG_OF_BOARD_SETUP */ 165