1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * CREDITS: Kim Phillips contribute to LIBFDT code 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #include <common.h> 14 #include <i2c.h> 15 #include <asm/io.h> 16 #include <asm/fsl_serdes.h> 17 #include <spd_sdram.h> 18 #if defined(CONFIG_OF_LIBFDT) 19 #include <libfdt.h> 20 #endif 21 #if defined(CONFIG_PQ_MDS_PIB) 22 #include "../common/pq-mds-pib.h" 23 #endif 24 25 int board_early_init_f(void) 26 { 27 u8 *bcsr = (u8 *)CFG_BCSR; 28 29 /* Enable flash write */ 30 bcsr[0x9] &= ~0x04; 31 /* Clear all of the interrupt of BCSR */ 32 bcsr[0xe] = 0xff; 33 34 #ifdef CONFIG_FSL_SERDES 35 immap_t *immr = (immap_t *)CFG_IMMR; 36 u32 spridr = in_be32(&immr->sysconf.spridr); 37 38 /* we check only part num, and don't look for CPU revisions */ 39 switch (spridr >> 16) { 40 case SPR_8379E_REV10 >> 16: 41 case SPR_8379_REV10 >> 16: 42 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, 43 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 44 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, 45 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 46 break; 47 case SPR_8378E_REV10 >> 16: 48 case SPR_8378_REV10 >> 16: 49 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, 50 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 51 break; 52 case SPR_8377E_REV10 >> 16: 53 case SPR_8377_REV10 >> 16: 54 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, 55 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 56 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, 57 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 58 break; 59 default: 60 printf("serdes not configured: unknown CPU part number: " 61 "%04x\n", spridr >> 16); 62 break; 63 } 64 #endif /* CONFIG_FSL_SERDES */ 65 return 0; 66 } 67 68 int board_early_init_r(void) 69 { 70 #ifdef CONFIG_PQ_MDS_PIB 71 pib_init(); 72 #endif 73 return 0; 74 } 75 76 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 77 extern void ddr_enable_ecc(unsigned int dram_size); 78 #endif 79 int fixed_sdram(void); 80 81 long int initdram(int board_type) 82 { 83 volatile immap_t *im = (immap_t *) CFG_IMMR; 84 u32 msize = 0; 85 86 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 87 return -1; 88 89 #if defined(CONFIG_SPD_EEPROM) 90 msize = spd_sdram(); 91 #else 92 msize = fixed_sdram(); 93 #endif 94 95 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 96 /* Initialize DDR ECC byte */ 97 ddr_enable_ecc(msize * 1024 * 1024); 98 #endif 99 100 /* return total bus DDR size(bytes) */ 101 return (msize * 1024 * 1024); 102 } 103 104 #if !defined(CONFIG_SPD_EEPROM) 105 /************************************************************************* 106 * fixed sdram init -- doesn't use serial presence detect. 107 ************************************************************************/ 108 int fixed_sdram(void) 109 { 110 volatile immap_t *im = (immap_t *) CFG_IMMR; 111 u32 msize = CFG_DDR_SIZE * 1024 * 1024; 112 u32 msize_log2 = __ilog2(msize); 113 114 im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; 115 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 116 117 #if (CFG_DDR_SIZE != 512) 118 #warning Currenly any ddr size other than 512 is not supported 119 #endif 120 im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; 121 udelay(50000); 122 123 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; 124 udelay(1000); 125 126 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; 127 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; 128 udelay(1000); 129 130 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 131 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 132 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 133 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 134 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 135 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 136 im->ddr.sdram_mode = CFG_DDR_MODE; 137 im->ddr.sdram_mode2 = CFG_DDR_MODE2; 138 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 139 __asm__ __volatile__("sync"); 140 udelay(1000); 141 142 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 143 udelay(2000); 144 return CFG_DDR_SIZE; 145 } 146 #endif /*!CFG_SPD_EEPROM */ 147 148 int checkboard(void) 149 { 150 puts("Board: Freescale MPC837xEMDS\n"); 151 return 0; 152 } 153 154 #if defined(CONFIG_OF_BOARD_SETUP) 155 void ft_board_setup(void *blob, bd_t *bd) 156 { 157 ft_cpu_setup(blob, bd); 158 #ifdef CONFIG_PCI 159 ft_pci_setup(blob, bd); 160 #endif 161 } 162 #endif /* CONFIG_OF_BOARD_SETUP */ 163