1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * CREDITS: Kim Phillips contribute to LIBFDT code 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #include <common.h> 14 #include <i2c.h> 15 #include <spd.h> 16 #if defined(CONFIG_SPD_EEPROM) 17 #include <spd_sdram.h> 18 #endif 19 #if defined(CONFIG_OF_FLAT_TREE) 20 #include <ft_build.h> 21 #elif defined(CONFIG_OF_LIBFDT) 22 #include <libfdt.h> 23 #endif 24 #if defined(CONFIG_PQ_MDS_PIB) 25 #include "../common/pq-mds-pib.h" 26 #endif 27 28 int board_early_init_f(void) 29 { 30 u8 *bcsr = (u8 *)CFG_BCSR; 31 32 /* Enable flash write */ 33 bcsr[0x9] &= ~0x04; 34 /* Clear all of the interrupt of BCSR */ 35 bcsr[0xe] = 0xff; 36 37 return 0; 38 } 39 40 int board_early_init_r(void) 41 { 42 #ifdef CONFIG_PQ_MDS_PIB 43 pib_init(); 44 #endif 45 return 0; 46 } 47 48 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 49 extern void ddr_enable_ecc(unsigned int dram_size); 50 #endif 51 int fixed_sdram(void); 52 53 long int initdram(int board_type) 54 { 55 volatile immap_t *im = (immap_t *) CFG_IMMR; 56 u32 msize = 0; 57 58 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 59 return -1; 60 61 #if defined(CONFIG_SPD_EEPROM) 62 msize = spd_sdram(); 63 #else 64 msize = fixed_sdram(); 65 #endif 66 67 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 68 /* Initialize DDR ECC byte */ 69 ddr_enable_ecc(msize * 1024 * 1024); 70 #endif 71 72 /* return total bus DDR size(bytes) */ 73 return (msize * 1024 * 1024); 74 } 75 76 #if !defined(CONFIG_SPD_EEPROM) 77 /************************************************************************* 78 * fixed sdram init -- doesn't use serial presence detect. 79 ************************************************************************/ 80 int fixed_sdram(void) 81 { 82 volatile immap_t *im = (immap_t *) CFG_IMMR; 83 u32 msize = CFG_DDR_SIZE * 1024 * 1024; 84 u32 msize_log2 = __ilog2(msize); 85 86 im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; 87 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 88 89 #if (CFG_DDR_SIZE != 512) 90 #warning Currenly any ddr size other than 512 is not supported 91 #endif 92 im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; 93 udelay(50000); 94 95 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; 96 udelay(1000); 97 98 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; 99 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; 100 udelay(1000); 101 102 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 103 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 104 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 105 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 106 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 107 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 108 im->ddr.sdram_mode = CFG_DDR_MODE; 109 im->ddr.sdram_mode2 = CFG_DDR_MODE2; 110 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 111 __asm__ __volatile__("sync"); 112 udelay(1000); 113 114 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 115 udelay(2000); 116 return CFG_DDR_SIZE; 117 } 118 #endif /*!CFG_SPD_EEPROM */ 119 120 int checkboard(void) 121 { 122 puts("Board: Freescale MPC837xEMDS\n"); 123 return 0; 124 } 125 126 #if defined(CONFIG_OF_BOARD_SETUP) 127 void ft_board_setup(void *blob, bd_t *bd) 128 { 129 #if defined(CONFIG_OF_FLAT_TREE) 130 u32 *p; 131 int len; 132 133 p = ft_get_prop(blob, "/memory/reg", &len); 134 if (p != NULL) { 135 *p++ = cpu_to_be32(bd->bi_memstart); 136 *p = cpu_to_be32(bd->bi_memsize); 137 } 138 #endif 139 ft_cpu_setup(blob, bd); 140 #ifdef CONFIG_PCI 141 ft_pci_setup(blob, bd); 142 #endif 143 } 144 #endif /* CONFIG_OF_BOARD_SETUP */ 145