119580e66SDave Liu /* 219580e66SDave Liu * Copyright (C) 2007 Freescale Semiconductor, Inc. 319580e66SDave Liu * Dave Liu <daveliu@freescale.com> 419580e66SDave Liu * 519580e66SDave Liu * CREDITS: Kim Phillips contribute to LIBFDT code 619580e66SDave Liu * 719580e66SDave Liu * This program is free software; you can redistribute it and/or 819580e66SDave Liu * modify it under the terms of the GNU General Public License as 919580e66SDave Liu * published by the Free Software Foundation; either version 2 of 1019580e66SDave Liu * the License, or (at your option) any later version. 1119580e66SDave Liu */ 1219580e66SDave Liu 1319580e66SDave Liu #include <common.h> 1419580e66SDave Liu #include <i2c.h> 1519580e66SDave Liu #include <spd.h> 1619580e66SDave Liu #if defined(CONFIG_SPD_EEPROM) 1719580e66SDave Liu #include <spd_sdram.h> 1819580e66SDave Liu #endif 19*b3458d2cSKim Phillips #if defined(CONFIG_OF_LIBFDT) 2019580e66SDave Liu #include <libfdt.h> 2119580e66SDave Liu #endif 2219580e66SDave Liu #if defined(CONFIG_PQ_MDS_PIB) 2319580e66SDave Liu #include "../common/pq-mds-pib.h" 2419580e66SDave Liu #endif 2519580e66SDave Liu 2619580e66SDave Liu int board_early_init_f(void) 2719580e66SDave Liu { 2819580e66SDave Liu u8 *bcsr = (u8 *)CFG_BCSR; 2919580e66SDave Liu 3019580e66SDave Liu /* Enable flash write */ 3119580e66SDave Liu bcsr[0x9] &= ~0x04; 3219580e66SDave Liu /* Clear all of the interrupt of BCSR */ 3319580e66SDave Liu bcsr[0xe] = 0xff; 3419580e66SDave Liu 3519580e66SDave Liu return 0; 3619580e66SDave Liu } 3719580e66SDave Liu 3819580e66SDave Liu int board_early_init_r(void) 3919580e66SDave Liu { 4019580e66SDave Liu #ifdef CONFIG_PQ_MDS_PIB 4119580e66SDave Liu pib_init(); 4219580e66SDave Liu #endif 4319580e66SDave Liu return 0; 4419580e66SDave Liu } 4519580e66SDave Liu 4619580e66SDave Liu #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 4719580e66SDave Liu extern void ddr_enable_ecc(unsigned int dram_size); 4819580e66SDave Liu #endif 4919580e66SDave Liu int fixed_sdram(void); 5019580e66SDave Liu 5119580e66SDave Liu long int initdram(int board_type) 5219580e66SDave Liu { 5319580e66SDave Liu volatile immap_t *im = (immap_t *) CFG_IMMR; 5419580e66SDave Liu u32 msize = 0; 5519580e66SDave Liu 5619580e66SDave Liu if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 5719580e66SDave Liu return -1; 5819580e66SDave Liu 5919580e66SDave Liu #if defined(CONFIG_SPD_EEPROM) 6019580e66SDave Liu msize = spd_sdram(); 6119580e66SDave Liu #else 6219580e66SDave Liu msize = fixed_sdram(); 6319580e66SDave Liu #endif 6419580e66SDave Liu 6519580e66SDave Liu #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) 6619580e66SDave Liu /* Initialize DDR ECC byte */ 6719580e66SDave Liu ddr_enable_ecc(msize * 1024 * 1024); 6819580e66SDave Liu #endif 6919580e66SDave Liu 7019580e66SDave Liu /* return total bus DDR size(bytes) */ 7119580e66SDave Liu return (msize * 1024 * 1024); 7219580e66SDave Liu } 7319580e66SDave Liu 7419580e66SDave Liu #if !defined(CONFIG_SPD_EEPROM) 7519580e66SDave Liu /************************************************************************* 7619580e66SDave Liu * fixed sdram init -- doesn't use serial presence detect. 7719580e66SDave Liu ************************************************************************/ 7819580e66SDave Liu int fixed_sdram(void) 7919580e66SDave Liu { 8019580e66SDave Liu volatile immap_t *im = (immap_t *) CFG_IMMR; 8119580e66SDave Liu u32 msize = CFG_DDR_SIZE * 1024 * 1024; 8219580e66SDave Liu u32 msize_log2 = __ilog2(msize); 8319580e66SDave Liu 8419580e66SDave Liu im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; 8519580e66SDave Liu im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); 8619580e66SDave Liu 8719580e66SDave Liu #if (CFG_DDR_SIZE != 512) 8819580e66SDave Liu #warning Currenly any ddr size other than 512 is not supported 8919580e66SDave Liu #endif 9019580e66SDave Liu im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; 9119580e66SDave Liu udelay(50000); 9219580e66SDave Liu 9319580e66SDave Liu im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; 9419580e66SDave Liu udelay(1000); 9519580e66SDave Liu 9619580e66SDave Liu im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; 9719580e66SDave Liu im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; 9819580e66SDave Liu udelay(1000); 9919580e66SDave Liu 10019580e66SDave Liu im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 10119580e66SDave Liu im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 10219580e66SDave Liu im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 10319580e66SDave Liu im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 10419580e66SDave Liu im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 10519580e66SDave Liu im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 10619580e66SDave Liu im->ddr.sdram_mode = CFG_DDR_MODE; 10719580e66SDave Liu im->ddr.sdram_mode2 = CFG_DDR_MODE2; 10819580e66SDave Liu im->ddr.sdram_interval = CFG_DDR_INTERVAL; 10919580e66SDave Liu __asm__ __volatile__("sync"); 11019580e66SDave Liu udelay(1000); 11119580e66SDave Liu 11219580e66SDave Liu im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 11319580e66SDave Liu udelay(2000); 11419580e66SDave Liu return CFG_DDR_SIZE; 11519580e66SDave Liu } 11619580e66SDave Liu #endif /*!CFG_SPD_EEPROM */ 11719580e66SDave Liu 11819580e66SDave Liu int checkboard(void) 11919580e66SDave Liu { 12019580e66SDave Liu puts("Board: Freescale MPC837xEMDS\n"); 12119580e66SDave Liu return 0; 12219580e66SDave Liu } 12319580e66SDave Liu 12419580e66SDave Liu #if defined(CONFIG_OF_BOARD_SETUP) 12519580e66SDave Liu void ft_board_setup(void *blob, bd_t *bd) 12619580e66SDave Liu { 12719580e66SDave Liu ft_cpu_setup(blob, bd); 12819580e66SDave Liu #ifdef CONFIG_PCI 12919580e66SDave Liu ft_pci_setup(blob, bd); 13019580e66SDave Liu #endif 13119580e66SDave Liu } 13219580e66SDave Liu #endif /* CONFIG_OF_BOARD_SETUP */ 133