1 /* 2 * See file CREDITS for list of people who contributed to this 3 * project. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 * 20 */ 21 22 #include <asm/mmu.h> 23 #include <common.h> 24 #include <asm/global_data.h> 25 #include <pci.h> 26 #include <asm/mpc8349_pci.h> 27 #include <i2c.h> 28 #if defined(CONFIG_OF_FLAT_TREE) 29 #include <ft_build.h> 30 #elif defined(CONFIG_OF_LIBFDT) 31 #include <libfdt.h> 32 #include <fdt_support.h> 33 #endif 34 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #ifdef CONFIG_PCI 39 40 /* System RAM mapped to PCI space */ 41 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE 42 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE 43 44 #ifndef CONFIG_PCI_PNP 45 static struct pci_config_table pci_mpc8349emds_config_table[] = { 46 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 47 PCI_IDSEL_NUMBER, PCI_ANY_ID, 48 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 49 PCI_ENET0_MEMADDR, 50 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 51 } 52 }, 53 {} 54 }; 55 #endif 56 57 static struct pci_controller pci_hose[] = { 58 { 59 #ifndef CONFIG_PCI_PNP 60 config_table:pci_mpc8349emds_config_table, 61 #endif 62 }, 63 { 64 #ifndef CONFIG_PCI_PNP 65 config_table:pci_mpc8349emds_config_table, 66 #endif 67 } 68 }; 69 70 /************************************************************************** 71 * 72 * pib_init() -- initialize the PCA9555PW IO expander on the PIB board 73 * 74 */ 75 void 76 pib_init(void) 77 { 78 u8 val8, orig_i2c_bus; 79 /* 80 * Assign PIB PMC slot to desired PCI bus 81 */ 82 /* Switch temporarily to I2C bus #2 */ 83 orig_i2c_bus = i2c_get_bus_num(); 84 i2c_set_bus_num(1); 85 86 val8 = 0; 87 i2c_write(0x23, 0x6, 1, &val8, 1); 88 i2c_write(0x23, 0x7, 1, &val8, 1); 89 val8 = 0xff; 90 i2c_write(0x23, 0x2, 1, &val8, 1); 91 i2c_write(0x23, 0x3, 1, &val8, 1); 92 93 val8 = 0; 94 i2c_write(0x26, 0x6, 1, &val8, 1); 95 val8 = 0x34; 96 i2c_write(0x26, 0x7, 1, &val8, 1); 97 #if defined(PCI_64BIT) 98 val8 = 0xf4; /* PMC2:PCI1/64-bit */ 99 #elif defined(PCI_ALL_PCI1) 100 val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ 101 #elif defined(PCI_ONE_PCI1) 102 val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ 103 #else 104 val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ 105 #endif 106 i2c_write(0x26, 0x2, 1, &val8, 1); 107 val8 = 0xff; 108 i2c_write(0x26, 0x3, 1, &val8, 1); 109 val8 = 0; 110 i2c_write(0x27, 0x6, 1, &val8, 1); 111 i2c_write(0x27, 0x7, 1, &val8, 1); 112 val8 = 0xff; 113 i2c_write(0x27, 0x2, 1, &val8, 1); 114 val8 = 0xef; 115 i2c_write(0x27, 0x3, 1, &val8, 1); 116 asm("eieio"); 117 118 #if defined(PCI_64BIT) 119 printf("PCI1: 64-bit on PMC2\n"); 120 #elif defined(PCI_ALL_PCI1) 121 printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); 122 #elif defined(PCI_ONE_PCI1) 123 printf("PCI1: 32-bit on PMC1\n"); 124 printf("PCI2: 32-bit on PMC2, PMC3\n"); 125 #else 126 printf("PCI1: 32-bit on PMC1, PMC2\n"); 127 printf("PCI2: 32-bit on PMC3\n"); 128 #endif 129 /* Reset to original I2C bus */ 130 i2c_set_bus_num(orig_i2c_bus); 131 } 132 133 /************************************************************************** 134 * pci_init_board() 135 * 136 * NOTICE: PCI2 is not currently supported 137 * 138 */ 139 void 140 pci_init_board(void) 141 { 142 volatile immap_t * immr; 143 volatile clk83xx_t * clk; 144 volatile law83xx_t * pci_law; 145 volatile pot83xx_t * pci_pot; 146 volatile pcictrl83xx_t * pci_ctrl; 147 volatile pciconf83xx_t * pci_conf; 148 u16 reg16; 149 u32 reg32; 150 u32 dev; 151 struct pci_controller * hose; 152 153 immr = (immap_t *)CFG_IMMR; 154 clk = (clk83xx_t *)&immr->clk; 155 pci_law = immr->sysconf.pcilaw; 156 pci_pot = immr->ios.pot; 157 pci_ctrl = immr->pci_ctrl; 158 pci_conf = immr->pci_conf; 159 160 hose = &pci_hose[0]; 161 162 pib_init(); 163 164 /* 165 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode 166 */ 167 168 reg32 = clk->occr; 169 udelay(2000); 170 clk->occr = 0xff000000; 171 udelay(2000); 172 173 /* 174 * Release PCI RST Output signal 175 */ 176 pci_ctrl[0].gcr = 0; 177 udelay(2000); 178 pci_ctrl[0].gcr = 1; 179 180 #ifdef CONFIG_MPC83XX_PCI2 181 pci_ctrl[1].gcr = 0; 182 udelay(2000); 183 pci_ctrl[1].gcr = 1; 184 #endif 185 186 /* We need to wait at least a 1sec based on PCI specs */ 187 { 188 int i; 189 190 for (i = 0; i < 1000; ++i) 191 udelay (1000); 192 } 193 194 /* 195 * Configure PCI Local Access Windows 196 */ 197 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; 198 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; 199 200 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; 201 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; 202 203 /* 204 * Configure PCI Outbound Translation Windows 205 */ 206 207 /* PCI1 mem space - prefetch */ 208 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; 209 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; 210 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); 211 212 /* PCI1 IO space */ 213 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; 214 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; 215 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); 216 217 /* PCI1 mmio - non-prefetch mem space */ 218 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; 219 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; 220 pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); 221 222 /* 223 * Configure PCI Inbound Translation Windows 224 */ 225 226 /* we need RAM mapped to PCI space for the devices to 227 * access main memory */ 228 pci_ctrl[0].pitar1 = 0x0; 229 pci_ctrl[0].pibar1 = 0x0; 230 pci_ctrl[0].piebar1 = 0x0; 231 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); 232 233 hose->first_busno = 0; 234 hose->last_busno = 0xff; 235 236 /* PCI memory prefetch space */ 237 pci_set_region(hose->regions + 0, 238 CFG_PCI1_MEM_BASE, 239 CFG_PCI1_MEM_PHYS, 240 CFG_PCI1_MEM_SIZE, 241 PCI_REGION_MEM|PCI_REGION_PREFETCH); 242 243 /* PCI memory space */ 244 pci_set_region(hose->regions + 1, 245 CFG_PCI1_MMIO_BASE, 246 CFG_PCI1_MMIO_PHYS, 247 CFG_PCI1_MMIO_SIZE, 248 PCI_REGION_MEM); 249 250 /* PCI IO space */ 251 pci_set_region(hose->regions + 2, 252 CFG_PCI1_IO_BASE, 253 CFG_PCI1_IO_PHYS, 254 CFG_PCI1_IO_SIZE, 255 PCI_REGION_IO); 256 257 /* System memory space */ 258 pci_set_region(hose->regions + 3, 259 CONFIG_PCI_SYS_MEM_BUS, 260 CONFIG_PCI_SYS_MEM_PHYS, 261 gd->ram_size, 262 PCI_REGION_MEM | PCI_REGION_MEMORY); 263 264 hose->region_count = 4; 265 266 pci_setup_indirect(hose, 267 (CFG_IMMR+0x8300), 268 (CFG_IMMR+0x8304)); 269 270 pci_register_hose(hose); 271 272 /* 273 * Write to Command register 274 */ 275 reg16 = 0xff; 276 dev = PCI_BDF(hose->first_busno, 0, 0); 277 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); 278 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 279 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); 280 281 /* 282 * Clear non-reserved bits in status register. 283 */ 284 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); 285 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 286 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 287 288 #ifdef CONFIG_PCI_SCAN_SHOW 289 printf("PCI: Bus Dev VenId DevId Class Int\n"); 290 #endif 291 /* 292 * Hose scan. 293 */ 294 hose->last_busno = pci_hose_scan(hose); 295 296 #ifdef CONFIG_MPC83XX_PCI2 297 hose = &pci_hose[1]; 298 299 /* 300 * Configure PCI Outbound Translation Windows 301 */ 302 303 /* PCI2 mem space - prefetch */ 304 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; 305 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; 306 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); 307 308 /* PCI2 IO space */ 309 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; 310 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; 311 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); 312 313 /* PCI2 mmio - non-prefetch mem space */ 314 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; 315 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; 316 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); 317 318 /* 319 * Configure PCI Inbound Translation Windows 320 */ 321 322 /* we need RAM mapped to PCI space for the devices to 323 * access main memory */ 324 pci_ctrl[1].pitar1 = 0x0; 325 pci_ctrl[1].pibar1 = 0x0; 326 pci_ctrl[1].piebar1 = 0x0; 327 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); 328 329 hose->first_busno = pci_hose[0].last_busno + 1; 330 hose->last_busno = 0xff; 331 332 /* PCI memory prefetch space */ 333 pci_set_region(hose->regions + 0, 334 CFG_PCI2_MEM_BASE, 335 CFG_PCI2_MEM_PHYS, 336 CFG_PCI2_MEM_SIZE, 337 PCI_REGION_MEM|PCI_REGION_PREFETCH); 338 339 /* PCI memory space */ 340 pci_set_region(hose->regions + 1, 341 CFG_PCI2_MMIO_BASE, 342 CFG_PCI2_MMIO_PHYS, 343 CFG_PCI2_MMIO_SIZE, 344 PCI_REGION_MEM); 345 346 /* PCI IO space */ 347 pci_set_region(hose->regions + 2, 348 CFG_PCI2_IO_BASE, 349 CFG_PCI2_IO_PHYS, 350 CFG_PCI2_IO_SIZE, 351 PCI_REGION_IO); 352 353 /* System memory space */ 354 pci_set_region(hose->regions + 3, 355 CONFIG_PCI_SYS_MEM_BUS, 356 CONFIG_PCI_SYS_MEM_PHYS, 357 gd->ram_size, 358 PCI_REGION_MEM | PCI_REGION_MEMORY); 359 360 hose->region_count = 4; 361 362 pci_setup_indirect(hose, 363 (CFG_IMMR+0x8380), 364 (CFG_IMMR+0x8384)); 365 366 pci_register_hose(hose); 367 368 /* 369 * Write to Command register 370 */ 371 reg16 = 0xff; 372 dev = PCI_BDF(hose->first_busno, 0, 0); 373 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); 374 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 375 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); 376 377 /* 378 * Clear non-reserved bits in status register. 379 */ 380 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); 381 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); 382 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); 383 384 /* 385 * Hose scan. 386 */ 387 hose->last_busno = pci_hose_scan(hose); 388 #endif 389 390 } 391 392 #if defined(CONFIG_OF_LIBFDT) 393 void ft_pci_setup(void *blob, bd_t *bd) 394 { 395 int nodeoffset; 396 int tmp[2]; 397 const char *path; 398 399 nodeoffset = fdt_path_offset(blob, "/aliases"); 400 if (nodeoffset >= 0) { 401 path = fdt_getprop(blob, nodeoffset, "pci0", NULL); 402 if (path) { 403 tmp[0] = cpu_to_be32(pci_hose[0].first_busno); 404 tmp[1] = cpu_to_be32(pci_hose[0].last_busno); 405 do_fixup_by_path(blob, path, "bus-range", 406 &tmp, sizeof(tmp), 1); 407 408 tmp[0] = cpu_to_be32(gd->pci_clk); 409 do_fixup_by_path(blob, path, "clock-frequency", 410 &tmp, sizeof(tmp[0]), 1); 411 } 412 #ifdef CONFIG_MPC83XX_PCI2 413 path = fdt_getprop(blob, nodeoffset, "pci1", NULL); 414 if (path) { 415 tmp[0] = cpu_to_be32(pci_hose[0].first_busno); 416 tmp[1] = cpu_to_be32(pci_hose[0].last_busno); 417 do_fixup_by_path(blob, path, "bus-range", 418 &tmp, sizeof(tmp), 1); 419 420 tmp[0] = cpu_to_be32(gd->pci_clk); 421 do_fixup_by_path(blob, path, "clock-frequency", 422 &tmp, sizeof(tmp[0]), 1); 423 } 424 #endif 425 } 426 } 427 #elif defined(CONFIG_OF_FLAT_TREE) 428 void 429 ft_pci_setup(void *blob, bd_t *bd) 430 { 431 u32 *p; 432 int len; 433 434 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); 435 if (p != NULL) { 436 p[0] = pci_hose[0].first_busno; 437 p[1] = pci_hose[0].last_busno; 438 } 439 440 #ifdef CONFIG_MPC83XX_PCI2 441 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); 442 if (p != NULL) { 443 p[0] = pci_hose[1].first_busno; 444 p[1] = pci_hose[1].last_busno; 445 } 446 #endif 447 } 448 #endif /* CONFIG_OF_FLAT_TREE */ 449 #endif /* CONFIG_PCI */ 450