1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * Michael Barkowski <michael.barkowski@freescale.com> 5 * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation. 10 */ 11 12 #include <common.h> 13 #include <ioports.h> 14 #include <mpc83xx.h> 15 #include <i2c.h> 16 #include <spd.h> 17 #include <miiphy.h> 18 #include <command.h> 19 #include <libfdt.h> 20 #if defined(CONFIG_PCI) 21 #include <pci.h> 22 #endif 23 #if defined(CONFIG_SPD_EEPROM) 24 #include <spd_sdram.h> 25 #else 26 #include <asm/mmu.h> 27 #endif 28 29 const qe_iop_conf_t qe_iop_conf_tab[] = { 30 /* UCC3 */ 31 {1, 0, 1, 0, 1}, /* TxD0 */ 32 {1, 1, 1, 0, 1}, /* TxD1 */ 33 {1, 2, 1, 0, 1}, /* TxD2 */ 34 {1, 3, 1, 0, 1}, /* TxD3 */ 35 {1, 9, 1, 0, 1}, /* TxER */ 36 {1, 12, 1, 0, 1}, /* TxEN */ 37 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ 38 39 {1, 4, 2, 0, 1}, /* RxD0 */ 40 {1, 5, 2, 0, 1}, /* RxD1 */ 41 {1, 6, 2, 0, 1}, /* RxD2 */ 42 {1, 7, 2, 0, 1}, /* RxD3 */ 43 {1, 8, 2, 0, 1}, /* RxER */ 44 {1, 10, 2, 0, 1}, /* RxDV */ 45 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ 46 {1, 11, 2, 0, 1}, /* COL */ 47 {1, 13, 2, 0, 1}, /* CRS */ 48 49 /* UCC2 */ 50 {0, 18, 1, 0, 1}, /* TxD0 */ 51 {0, 19, 1, 0, 1}, /* TxD1 */ 52 {0, 20, 1, 0, 1}, /* TxD2 */ 53 {0, 21, 1, 0, 1}, /* TxD3 */ 54 {0, 27, 1, 0, 1}, /* TxER */ 55 {0, 30, 1, 0, 1}, /* TxEN */ 56 {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */ 57 58 {0, 22, 2, 0, 1}, /* RxD0 */ 59 {0, 23, 2, 0, 1}, /* RxD1 */ 60 {0, 24, 2, 0, 1}, /* RxD2 */ 61 {0, 25, 2, 0, 1}, /* RxD3 */ 62 {0, 26, 1, 0, 1}, /* RxER */ 63 {0, 28, 2, 0, 1}, /* Rx_DV */ 64 {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */ 65 {0, 29, 2, 0, 1}, /* COL */ 66 {0, 31, 2, 0, 1}, /* CRS */ 67 68 {3, 4, 3, 0, 2}, /* MDIO */ 69 {3, 5, 1, 0, 2}, /* MDC */ 70 71 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 72 }; 73 74 int board_early_init_f(void) 75 { 76 return 0; 77 } 78 79 int fixed_sdram(void); 80 81 long int initdram(int board_type) 82 { 83 volatile immap_t *im = (immap_t *) CFG_IMMR; 84 u32 msize = 0; 85 86 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 87 return -1; 88 89 /* DDR SDRAM - Main SODIMM */ 90 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; 91 92 msize = fixed_sdram(); 93 94 puts("\n DDR RAM: "); 95 96 /* return total bus SDRAM size(bytes) -- DDR */ 97 return (msize * 1024 * 1024); 98 } 99 100 /************************************************************************* 101 * fixed sdram init -- doesn't use serial presence detect. 102 ************************************************************************/ 103 int fixed_sdram(void) 104 { 105 volatile immap_t *im = (immap_t *) CFG_IMMR; 106 u32 msize = 0; 107 u32 ddr_size; 108 u32 ddr_size_log2; 109 110 msize = CFG_DDR_SIZE; 111 for (ddr_size = msize << 20, ddr_size_log2 = 0; 112 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { 113 if (ddr_size & 1) { 114 return -1; 115 } 116 } 117 im->sysconf.ddrlaw[0].ar = 118 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 119 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; 120 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; 121 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; 122 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 123 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 124 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 125 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 126 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 127 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 128 im->ddr.sdram_mode = CFG_DDR_MODE; 129 im->ddr.sdram_mode2 = CFG_DDR_MODE2; 130 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 131 __asm__ __volatile__ ("sync"); 132 udelay(200); 133 134 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 135 __asm__ __volatile__ ("sync"); 136 return msize; 137 } 138 139 int checkboard(void) 140 { 141 puts("Board: Freescale MPC8323ERDB\n"); 142 return 0; 143 } 144 145 static struct pci_region pci_regions[] = { 146 { 147 bus_start: CFG_PCI1_MEM_BASE, 148 phys_start: CFG_PCI1_MEM_PHYS, 149 size: CFG_PCI1_MEM_SIZE, 150 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 151 }, 152 { 153 bus_start: CFG_PCI1_MMIO_BASE, 154 phys_start: CFG_PCI1_MMIO_PHYS, 155 size: CFG_PCI1_MMIO_SIZE, 156 flags: PCI_REGION_MEM 157 }, 158 { 159 bus_start: CFG_PCI1_IO_BASE, 160 phys_start: CFG_PCI1_IO_PHYS, 161 size: CFG_PCI1_IO_SIZE, 162 flags: PCI_REGION_IO 163 } 164 }; 165 166 void pci_init_board(void) 167 { 168 volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; 169 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 170 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 171 struct pci_region *reg[] = { pci_regions }; 172 173 /* Enable all 3 PCI_CLK_OUTPUTs. */ 174 clk->occr |= 0xe0000000; 175 176 /* Configure PCI Local Access Windows */ 177 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; 178 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; 179 180 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; 181 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; 182 183 mpc83xx_pci_init(1, reg, 0); 184 } 185 186 #if defined(CONFIG_OF_BOARD_SETUP) 187 void 188 ft_board_setup(void *blob, bd_t *bd) 189 { 190 ft_cpu_setup(blob, bd); 191 #ifdef CONFIG_PCI 192 ft_pci_setup(blob, bd); 193 #endif 194 } 195 #endif /* CONFIG_OF_BOARD_SETUP */ 196