1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * Michael Barkowski <michael.barkowski@freescale.com> 5 * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation. 10 */ 11 12 #include <common.h> 13 #include <ioports.h> 14 #include <mpc83xx.h> 15 #include <i2c.h> 16 #include <spd.h> 17 #include <miiphy.h> 18 #include <command.h> 19 #include <libfdt.h> 20 #include <libfdt_env.h> 21 #if defined(CONFIG_PCI) 22 #include <pci.h> 23 #endif 24 #if defined(CONFIG_SPD_EEPROM) 25 #include <spd_sdram.h> 26 #else 27 #include <asm/mmu.h> 28 #endif 29 30 const qe_iop_conf_t qe_iop_conf_tab[] = { 31 /* UCC3 */ 32 {1, 0, 1, 0, 1}, /* TxD0 */ 33 {1, 1, 1, 0, 1}, /* TxD1 */ 34 {1, 2, 1, 0, 1}, /* TxD2 */ 35 {1, 3, 1, 0, 1}, /* TxD3 */ 36 {1, 9, 1, 0, 1}, /* TxER */ 37 {1, 12, 1, 0, 1}, /* TxEN */ 38 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ 39 40 {1, 4, 2, 0, 1}, /* RxD0 */ 41 {1, 5, 2, 0, 1}, /* RxD1 */ 42 {1, 6, 2, 0, 1}, /* RxD2 */ 43 {1, 7, 2, 0, 1}, /* RxD3 */ 44 {1, 8, 2, 0, 1}, /* RxER */ 45 {1, 10, 2, 0, 1}, /* RxDV */ 46 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ 47 {1, 11, 2, 0, 1}, /* COL */ 48 {1, 13, 2, 0, 1}, /* CRS */ 49 50 /* UCC2 */ 51 {0, 18, 1, 0, 1}, /* TxD0 */ 52 {0, 19, 1, 0, 1}, /* TxD1 */ 53 {0, 20, 1, 0, 1}, /* TxD2 */ 54 {0, 21, 1, 0, 1}, /* TxD3 */ 55 {0, 27, 1, 0, 1}, /* TxER */ 56 {0, 30, 1, 0, 1}, /* TxEN */ 57 {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */ 58 59 {0, 22, 2, 0, 1}, /* RxD0 */ 60 {0, 23, 2, 0, 1}, /* RxD1 */ 61 {0, 24, 2, 0, 1}, /* RxD2 */ 62 {0, 25, 2, 0, 1}, /* RxD3 */ 63 {0, 26, 1, 0, 1}, /* RxER */ 64 {0, 28, 2, 0, 1}, /* Rx_DV */ 65 {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */ 66 {0, 29, 2, 0, 1}, /* COL */ 67 {0, 31, 2, 0, 1}, /* CRS */ 68 69 {3, 4, 3, 0, 2}, /* MDIO */ 70 {3, 5, 1, 0, 2}, /* MDC */ 71 72 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ 73 }; 74 75 int board_early_init_f(void) 76 { 77 return 0; 78 } 79 80 int fixed_sdram(void); 81 82 long int initdram(int board_type) 83 { 84 volatile immap_t *im = (immap_t *) CFG_IMMR; 85 u32 msize = 0; 86 87 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) 88 return -1; 89 90 /* DDR SDRAM - Main SODIMM */ 91 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; 92 93 msize = fixed_sdram(); 94 95 puts("\n DDR RAM: "); 96 97 /* return total bus SDRAM size(bytes) -- DDR */ 98 return (msize * 1024 * 1024); 99 } 100 101 /************************************************************************* 102 * fixed sdram init -- doesn't use serial presence detect. 103 ************************************************************************/ 104 int fixed_sdram(void) 105 { 106 volatile immap_t *im = (immap_t *) CFG_IMMR; 107 u32 msize = 0; 108 u32 ddr_size; 109 u32 ddr_size_log2; 110 111 msize = CFG_DDR_SIZE; 112 for (ddr_size = msize << 20, ddr_size_log2 = 0; 113 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { 114 if (ddr_size & 1) { 115 return -1; 116 } 117 } 118 im->sysconf.ddrlaw[0].ar = 119 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); 120 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; 121 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; 122 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; 123 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; 124 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; 125 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; 126 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; 127 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; 128 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; 129 im->ddr.sdram_mode = CFG_DDR_MODE; 130 im->ddr.sdram_mode2 = CFG_DDR_MODE2; 131 im->ddr.sdram_interval = CFG_DDR_INTERVAL; 132 __asm__ __volatile__ ("sync"); 133 udelay(200); 134 135 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 136 __asm__ __volatile__ ("sync"); 137 return msize; 138 } 139 140 int checkboard(void) 141 { 142 puts("Board: Freescale MPC8323ERDB\n"); 143 return 0; 144 } 145 146 static struct pci_region pci_regions[] = { 147 { 148 bus_start: CFG_PCI1_MEM_BASE, 149 phys_start: CFG_PCI1_MEM_PHYS, 150 size: CFG_PCI1_MEM_SIZE, 151 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 152 }, 153 { 154 bus_start: CFG_PCI1_MMIO_BASE, 155 phys_start: CFG_PCI1_MMIO_PHYS, 156 size: CFG_PCI1_MMIO_SIZE, 157 flags: PCI_REGION_MEM 158 }, 159 { 160 bus_start: CFG_PCI1_IO_BASE, 161 phys_start: CFG_PCI1_IO_PHYS, 162 size: CFG_PCI1_IO_SIZE, 163 flags: PCI_REGION_IO 164 } 165 }; 166 167 void pci_init_board(void) 168 { 169 volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; 170 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 171 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 172 struct pci_region *reg[] = { pci_regions }; 173 174 /* Enable all 3 PCI_CLK_OUTPUTs. */ 175 clk->occr |= 0xe0000000; 176 177 /* Configure PCI Local Access Windows */ 178 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; 179 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; 180 181 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; 182 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; 183 184 mpc83xx_pci_init(1, reg, 0); 185 } 186 187 #if defined(CONFIG_OF_BOARD_SETUP) 188 189 /* 190 * Prototypes of functions that we use. 191 */ 192 void ft_cpu_setup(void *blob, bd_t *bd); 193 194 #ifdef CONFIG_PCI 195 void ft_pci_setup(void *blob, bd_t *bd); 196 #endif 197 198 void 199 ft_board_setup(void *blob, bd_t *bd) 200 { 201 int nodeoffset; 202 int tmp[2]; 203 204 nodeoffset = fdt_find_node_by_path(blob, "/memory"); 205 if (nodeoffset >= 0) { 206 tmp[0] = cpu_to_be32(bd->bi_memstart); 207 tmp[1] = cpu_to_be32(bd->bi_memsize); 208 fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); 209 } 210 211 ft_cpu_setup(blob, bd); 212 213 #ifdef CONFIG_PCI 214 ft_pci_setup(blob, bd); 215 #endif 216 } 217 #endif /* CONFIG_OF_BOARD_SETUP */ 218