1 /* 2 * Copyright (C) 2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <hwconfig.h> 26 #include <i2c.h> 27 #include <spi.h> 28 #include <libfdt.h> 29 #include <fdt_support.h> 30 #include <pci.h> 31 #include <mpc83xx.h> 32 #include <vsc7385.h> 33 #include <netdev.h> 34 #include <asm/io.h> 35 #include <asm/fsl_serdes.h> 36 #include <asm/fsl_mpc83xx_serdes.h> 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 /* 41 * The following are used to control the SPI chip selects for the SPI command. 42 */ 43 #ifdef CONFIG_MPC8XXX_SPI 44 45 #define SPI_CS_MASK 0x00400000 46 47 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 48 { 49 return bus == 0 && cs == 0; 50 } 51 52 void spi_cs_activate(struct spi_slave *slave) 53 { 54 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 55 56 /* active low */ 57 clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); 58 } 59 60 void spi_cs_deactivate(struct spi_slave *slave) 61 { 62 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 63 64 /* inactive high */ 65 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); 66 } 67 #endif /* CONFIG_MPC8XXX_SPI */ 68 69 static u8 read_board_info(void) 70 { 71 u8 val8; 72 i2c_set_bus_num(0); 73 74 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) 75 return val8; 76 else 77 return 0; 78 } 79 80 int checkboard(void) 81 { 82 static const char * const rev_str[] = { 83 "1.0", 84 "<reserved>", 85 "<reserved>", 86 "<reserved>", 87 "<unknown>", 88 }; 89 u8 info; 90 int i; 91 92 info = read_board_info(); 93 i = (!info) ? 4 : info & 0x03; 94 95 printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]); 96 97 return 0; 98 } 99 100 static struct pci_region pcie_regions_0[] = { 101 { 102 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, 103 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, 104 .size = CONFIG_SYS_PCIE1_MEM_SIZE, 105 .flags = PCI_REGION_MEM, 106 }, 107 { 108 .bus_start = CONFIG_SYS_PCIE1_IO_BASE, 109 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, 110 .size = CONFIG_SYS_PCIE1_IO_SIZE, 111 .flags = PCI_REGION_IO, 112 }, 113 }; 114 115 void pci_init_board(void) 116 { 117 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 118 sysconf83xx_t *sysconf = &immr->sysconf; 119 law83xx_t *pcie_law = sysconf->pcielaw; 120 struct pci_region *pcie_reg[] = { pcie_regions_0 }; 121 122 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, 123 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); 124 125 /* Deassert the resets in the control register */ 126 out_be32(&sysconf->pecr1, 0xE0008000); 127 udelay(2000); 128 129 /* Configure PCI Express Local Access Windows */ 130 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); 131 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); 132 133 mpc83xx_pcie_init(1, pcie_reg); 134 } 135 /* 136 * Miscellaneous late-boot configurations 137 * 138 * If a VSC7385 microcode image is present, then upload it. 139 */ 140 int misc_init_r(void) 141 { 142 #ifdef CONFIG_MPC8XXX_SPI 143 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; 144 sysconf83xx_t *sysconf = &immr->sysconf; 145 146 /* 147 * Set proper bits in SICRH to allow SPI on header J8 148 * 149 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse 150 * switch. The pinmux configuration does not have a fine enough 151 * granularity to support both simultaneously. 152 */ 153 clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO); 154 puts("WARNING: SPI enabled, TSEC2 support is broken\n"); 155 156 /* Set header J8 SPI chip select output, disabled */ 157 setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK); 158 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); 159 #endif 160 161 #ifdef CONFIG_VSC7385_IMAGE 162 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, 163 CONFIG_VSC7385_IMAGE_SIZE)) { 164 puts("Failure uploading VSC7385 microcode.\n"); 165 return 1; 166 } 167 #endif 168 169 return 0; 170 } 171 #if defined(CONFIG_OF_BOARD_SETUP) 172 void ft_board_setup(void *blob, bd_t *bd) 173 { 174 ft_cpu_setup(blob, bd); 175 fdt_fixup_dr_usb(blob, bd); 176 } 177 #endif 178 179 int board_eth_init(bd_t *bis) 180 { 181 int rv, num_if = 0; 182 183 /* Initialize TSECs first */ 184 rv = cpu_eth_init(bis); 185 if (rv >= 0) 186 num_if += rv; 187 else 188 printf("ERROR: failed to initialize TSECs.\n"); 189 190 rv = pci_eth_init(bis); 191 if (rv >= 0) 192 num_if += rv; 193 else 194 printf("ERROR: failed to initialize PCI Ethernet.\n"); 195 196 return num_if; 197 } 198