11ac559d4STsiChungLiew /*
21ac559d4STsiChungLiew * (C) Copyright 2000-2003
31ac559d4STsiChungLiew * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
41ac559d4STsiChungLiew *
5aa0d99fcSAlison Wang * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
61ac559d4STsiChungLiew * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
71ac559d4STsiChungLiew *
81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+
91ac559d4STsiChungLiew */
101ac559d4STsiChungLiew
111ac559d4STsiChungLiew #include <config.h>
121ac559d4STsiChungLiew #include <common.h>
131ac559d4STsiChungLiew #include <asm/io.h>
141ac559d4STsiChungLiew #include <asm/immap.h>
151ac559d4STsiChungLiew
161ac559d4STsiChungLiew DECLARE_GLOBAL_DATA_PTR;
171ac559d4STsiChungLiew
181ac559d4STsiChungLiew #if defined(CONFIG_CMD_NAND)
191ac559d4STsiChungLiew #include <nand.h>
201ac559d4STsiChungLiew #include <linux/mtd/mtd.h>
211ac559d4STsiChungLiew
221ac559d4STsiChungLiew #define SET_CLE 0x10
231ac559d4STsiChungLiew #define SET_ALE 0x08
241ac559d4STsiChungLiew
nand_hwcontrol(struct mtd_info * mtdinfo,int cmd,unsigned int ctrl)25f64cb652SScott Wood static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
261ac559d4STsiChungLiew {
27*17cb4b8fSScott Wood struct nand_chip *this = mtd_to_nand(mtdinfo);
28e4f69d1bSTsiChung Liew volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
291ac559d4STsiChungLiew
30f64cb652SScott Wood if (ctrl & NAND_CTRL_CHANGE) {
31f64cb652SScott Wood ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
32f64cb652SScott Wood
33e4f69d1bSTsiChung Liew IO_ADDR_W &= ~(SET_ALE | SET_CLE);
34e4f69d1bSTsiChung Liew
35e4f69d1bSTsiChung Liew if (ctrl & NAND_NCE)
369017d932STsiChung Liew *nCE &= 0xFFFB;
379017d932STsiChung Liew else
38e4f69d1bSTsiChung Liew *nCE |= 0x0004;
399017d932STsiChung Liew
40f64cb652SScott Wood if (ctrl & NAND_CLE)
41f64cb652SScott Wood IO_ADDR_W |= SET_CLE;
42f64cb652SScott Wood if (ctrl & NAND_ALE)
43f64cb652SScott Wood IO_ADDR_W |= SET_ALE;
44f64cb652SScott Wood
45f64cb652SScott Wood this->IO_ADDR_W = (void *)IO_ADDR_W;
46f64cb652SScott Wood
471ac559d4STsiChungLiew }
481ac559d4STsiChungLiew
49f64cb652SScott Wood if (cmd != NAND_CMD_NONE)
50f64cb652SScott Wood writeb(cmd, this->IO_ADDR_W);
511ac559d4STsiChungLiew }
521ac559d4STsiChungLiew
board_nand_init(struct nand_chip * nand)531ac559d4STsiChungLiew int board_nand_init(struct nand_chip *nand)
541ac559d4STsiChungLiew {
55aa0d99fcSAlison Wang gpio_t *gpio = (gpio_t *) MMAP_GPIO;
56aa0d99fcSAlison Wang fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
571ac559d4STsiChungLiew
58aa0d99fcSAlison Wang clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
591ac559d4STsiChungLiew
60e4f69d1bSTsiChung Liew /*
61e4f69d1bSTsiChung Liew * set up pin configuration - enabled 2nd output buffer's signals
62e4f69d1bSTsiChung Liew * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
63e4f69d1bSTsiChung Liew * to use nCE signal
64e4f69d1bSTsiChung Liew */
65aa0d99fcSAlison Wang clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
66aa0d99fcSAlison Wang setbits_8(&gpio->pddr_timer, 0x08);
67aa0d99fcSAlison Wang setbits_8(&gpio->ppd_timer, 0x08);
68aa0d99fcSAlison Wang out_8(&gpio->pclrr_timer, 0);
69aa0d99fcSAlison Wang out_8(&gpio->podr_timer, 0);
701ac559d4STsiChungLiew
719017d932STsiChung Liew nand->chip_delay = 60;
72f64cb652SScott Wood nand->ecc.mode = NAND_ECC_SOFT;
73f64cb652SScott Wood nand->cmd_ctrl = nand_hwcontrol;
741ac559d4STsiChungLiew
751ac559d4STsiChungLiew return 0;
761ac559d4STsiChungLiew }
771ac559d4STsiChungLiew #endif
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