1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6 * Hayden Fraser (Hayden.Fraser@freescale.com) 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/immap.h> 13 #include <asm/io.h> 14 15 int checkboard(void) 16 { 17 puts("Board: "); 18 puts("Freescale MCF5253 EVBE\n"); 19 return 0; 20 }; 21 22 phys_size_t initdram(int board_type) 23 { 24 /* 25 * Check to see if the SDRAM has already been initialized 26 * by a run control tool 27 */ 28 if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { 29 u32 RC, dramsize; 30 31 RC = (CONFIG_SYS_CLK / 1000000) >> 1; 32 RC = (RC * 15) >> 4; 33 34 /* Initialize DRAM Control Register: DCR */ 35 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); 36 asm("nop"); 37 38 mbar_writeLong(MCFSIM_DACR0, 0x00002320); 39 asm("nop"); 40 41 /* Initialize DMR0 */ 42 dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; 43 mbar_writeLong(MCFSIM_DMR0, dramsize | 1); 44 asm("nop"); 45 46 mbar_writeLong(MCFSIM_DACR0, 0x00002328); 47 asm("nop"); 48 49 /* Write to this block to initiate precharge */ 50 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; 51 asm("nop"); 52 53 /* Set RE bit in DACR */ 54 mbar_writeLong(MCFSIM_DACR0, 55 mbar_readLong(MCFSIM_DACR0) | 0x8000); 56 asm("nop"); 57 58 /* Wait for at least 8 auto refresh cycles to occur */ 59 udelay(500); 60 61 /* Finish the configuration by issuing the MRS */ 62 mbar_writeLong(MCFSIM_DACR0, 63 mbar_readLong(MCFSIM_DACR0) | 0x0040); 64 asm("nop"); 65 66 *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; 67 } 68 69 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 70 } 71 72 int testdram(void) 73 { 74 /* TODO: XXX XXX XXX */ 75 printf("DRAM test not implemented!\n"); 76 77 return (0); 78 } 79 80 #ifdef CONFIG_CMD_IDE 81 #include <ata.h> 82 int ide_preinit(void) 83 { 84 return (0); 85 } 86 87 void ide_set_reset(int idereset) 88 { 89 atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; 90 long period; 91 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ 92 int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ 93 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ 94 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ 95 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ 96 {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ 97 }; 98 99 if (idereset) { 100 /* control reset */ 101 out_8(&ata->cr, 0); 102 udelay(100); 103 } else { 104 mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); 105 106 #define CALC_TIMING(t) (t + period - 1) / period 107 period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ 108 109 /*ata->ton = CALC_TIMING (180); */ 110 out_8(&ata->t1, CALC_TIMING(piotms[2][0])); 111 out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); 112 out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); 113 out_8(&ata->ta, CALC_TIMING(piotms[2][8])); 114 out_8(&ata->trd, CALC_TIMING(piotms[2][7])); 115 out_8(&ata->t4, CALC_TIMING(piotms[2][3])); 116 out_8(&ata->t9, CALC_TIMING(piotms[2][6])); 117 118 /* IORDY enable */ 119 out_8(&ata->cr, 0x40); 120 udelay(2000); 121 /* IORDY enable */ 122 setbits_8(&ata->cr, 0x01); 123 } 124 } 125 #endif /* CONFIG_CMD_IDE */ 126