1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6 * Hayden Fraser (Hayden.Fraser@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <asm/immap.h> 29 #include <asm/io.h> 30 31 int checkboard(void) 32 { 33 puts("Board: "); 34 puts("Freescale MCF5253 EVBE\n"); 35 return 0; 36 }; 37 38 phys_size_t initdram(int board_type) 39 { 40 /* 41 * Check to see if the SDRAM has already been initialized 42 * by a run control tool 43 */ 44 if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { 45 u32 RC, dramsize; 46 47 RC = (CONFIG_SYS_CLK / 1000000) >> 1; 48 RC = (RC * 15) >> 4; 49 50 /* Initialize DRAM Control Register: DCR */ 51 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); 52 asm("nop"); 53 54 mbar_writeLong(MCFSIM_DACR0, 0x00002320); 55 asm("nop"); 56 57 /* Initialize DMR0 */ 58 dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; 59 mbar_writeLong(MCFSIM_DMR0, dramsize | 1); 60 asm("nop"); 61 62 mbar_writeLong(MCFSIM_DACR0, 0x00002328); 63 asm("nop"); 64 65 /* Write to this block to initiate precharge */ 66 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; 67 asm("nop"); 68 69 /* Set RE bit in DACR */ 70 mbar_writeLong(MCFSIM_DACR0, 71 mbar_readLong(MCFSIM_DACR0) | 0x8000); 72 asm("nop"); 73 74 /* Wait for at least 8 auto refresh cycles to occur */ 75 udelay(500); 76 77 /* Finish the configuration by issuing the MRS */ 78 mbar_writeLong(MCFSIM_DACR0, 79 mbar_readLong(MCFSIM_DACR0) | 0x0040); 80 asm("nop"); 81 82 *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; 83 } 84 85 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 86 } 87 88 int testdram(void) 89 { 90 /* TODO: XXX XXX XXX */ 91 printf("DRAM test not implemented!\n"); 92 93 return (0); 94 } 95 96 #ifdef CONFIG_CMD_IDE 97 #include <ata.h> 98 int ide_preinit(void) 99 { 100 return (0); 101 } 102 103 void ide_set_reset(int idereset) 104 { 105 atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; 106 long period; 107 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ 108 int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ 109 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ 110 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ 111 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ 112 {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ 113 }; 114 115 if (idereset) { 116 /* control reset */ 117 out_8(&ata->cr, 0); 118 udelay(100); 119 } else { 120 mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); 121 122 #define CALC_TIMING(t) (t + period - 1) / period 123 period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ 124 125 /*ata->ton = CALC_TIMING (180); */ 126 out_8(&ata->t1, CALC_TIMING(piotms[2][0])); 127 out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); 128 out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); 129 out_8(&ata->ta, CALC_TIMING(piotms[2][8])); 130 out_8(&ata->trd, CALC_TIMING(piotms[2][7])); 131 out_8(&ata->t4, CALC_TIMING(piotms[2][3])); 132 out_8(&ata->t9, CALC_TIMING(piotms[2][6])); 133 134 /* IORDY enable */ 135 out_8(&ata->cr, 0x40); 136 udelay(2000); 137 /* IORDY enable */ 138 setbits_8(&ata->cr, 0x01); 139 } 140 } 141 #endif /* CONFIG_CMD_IDE */ 142