1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6 * Hayden Fraser (Hayden.Fraser@freescale.com) 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/immap.h> 13 #include <asm/io.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 int checkboard(void) 18 { 19 puts("Board: "); 20 puts("Freescale MCF5253 EVBE\n"); 21 return 0; 22 }; 23 24 int dram_init(void) 25 { 26 /* 27 * Check to see if the SDRAM has already been initialized 28 * by a run control tool 29 */ 30 if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { 31 u32 RC, dramsize; 32 33 RC = (CONFIG_SYS_CLK / 1000000) >> 1; 34 RC = (RC * 15) >> 4; 35 36 /* Initialize DRAM Control Register: DCR */ 37 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); 38 asm("nop"); 39 40 mbar_writeLong(MCFSIM_DACR0, 0x00002320); 41 asm("nop"); 42 43 /* Initialize DMR0 */ 44 dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; 45 mbar_writeLong(MCFSIM_DMR0, dramsize | 1); 46 asm("nop"); 47 48 mbar_writeLong(MCFSIM_DACR0, 0x00002328); 49 asm("nop"); 50 51 /* Write to this block to initiate precharge */ 52 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; 53 asm("nop"); 54 55 /* Set RE bit in DACR */ 56 mbar_writeLong(MCFSIM_DACR0, 57 mbar_readLong(MCFSIM_DACR0) | 0x8000); 58 asm("nop"); 59 60 /* Wait for at least 8 auto refresh cycles to occur */ 61 udelay(500); 62 63 /* Finish the configuration by issuing the MRS */ 64 mbar_writeLong(MCFSIM_DACR0, 65 mbar_readLong(MCFSIM_DACR0) | 0x0040); 66 asm("nop"); 67 68 *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; 69 } 70 71 gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 72 73 return 0; 74 } 75 76 int testdram(void) 77 { 78 /* TODO: XXX XXX XXX */ 79 printf("DRAM test not implemented!\n"); 80 81 return (0); 82 } 83 84 #ifdef CONFIG_CMD_IDE 85 #include <ata.h> 86 int ide_preinit(void) 87 { 88 return (0); 89 } 90 91 void ide_set_reset(int idereset) 92 { 93 atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; 94 long period; 95 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ 96 int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ 97 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ 98 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ 99 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ 100 {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ 101 }; 102 103 if (idereset) { 104 /* control reset */ 105 out_8(&ata->cr, 0); 106 udelay(100); 107 } else { 108 mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); 109 110 #define CALC_TIMING(t) (t + period - 1) / period 111 period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ 112 113 /*ata->ton = CALC_TIMING (180); */ 114 out_8(&ata->t1, CALC_TIMING(piotms[2][0])); 115 out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); 116 out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); 117 out_8(&ata->ta, CALC_TIMING(piotms[2][8])); 118 out_8(&ata->trd, CALC_TIMING(piotms[2][7])); 119 out_8(&ata->t4, CALC_TIMING(piotms[2][3])); 120 out_8(&ata->t9, CALC_TIMING(piotms[2][6])); 121 122 /* IORDY enable */ 123 out_8(&ata->cr, 0x40); 124 udelay(2000); 125 /* IORDY enable */ 126 setbits_8(&ata->cr, 0x01); 127 } 128 } 129 #endif /* CONFIG_CMD_IDE */ 130