1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <malloc.h> 8 #include <errno.h> 9 #include <netdev.h> 10 #include <fsl_ifc.h> 11 #include <fsl_ddr.h> 12 #include <asm/io.h> 13 #include <hwconfig.h> 14 #include <fdt_support.h> 15 #include <libfdt.h> 16 #include <fsl_debug_server.h> 17 #include <fsl-mc/fsl_mc.h> 18 #include <environment.h> 19 #include <i2c.h> 20 #include <asm/arch/soc.h> 21 #include <fsl_sec.h> 22 23 #include "../common/qixis.h" 24 #include "ls2080ardb_qixis.h" 25 26 #define PIN_MUX_SEL_SDHC 0x00 27 #define PIN_MUX_SEL_DSPI 0x0a 28 29 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 30 DECLARE_GLOBAL_DATA_PTR; 31 32 enum { 33 MUX_TYPE_SDHC, 34 MUX_TYPE_DSPI, 35 }; 36 37 unsigned long long get_qixis_addr(void) 38 { 39 unsigned long long addr; 40 41 if (gd->flags & GD_FLG_RELOC) 42 addr = QIXIS_BASE_PHYS; 43 else 44 addr = QIXIS_BASE_PHYS_EARLY; 45 46 /* 47 * IFC address under 256MB is mapped to 0x30000000, any address above 48 * is mapped to 0x5_10000000 up to 4GB. 49 */ 50 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 51 52 return addr; 53 } 54 55 int checkboard(void) 56 { 57 u8 sw; 58 char buf[15]; 59 60 cpu_name(buf); 61 printf("Board: %s-RDB, ", buf); 62 63 sw = QIXIS_READ(arch); 64 printf("Board Arch: V%d, ", sw >> 4); 65 printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 66 67 sw = QIXIS_READ(brdcfg[0]); 68 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 69 70 if (sw < 0x8) 71 printf("vBank: %d\n", sw); 72 else if (sw == 0x9) 73 puts("NAND\n"); 74 else 75 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 76 77 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 78 79 puts("SERDES1 Reference : "); 80 printf("Clock1 = 156.25MHz "); 81 printf("Clock2 = 156.25MHz"); 82 83 puts("\nSERDES2 Reference : "); 84 printf("Clock1 = 100MHz "); 85 printf("Clock2 = 100MHz\n"); 86 87 return 0; 88 } 89 90 unsigned long get_board_sys_clk(void) 91 { 92 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 93 94 switch (sysclk_conf & 0x0F) { 95 case QIXIS_SYSCLK_83: 96 return 83333333; 97 case QIXIS_SYSCLK_100: 98 return 100000000; 99 case QIXIS_SYSCLK_125: 100 return 125000000; 101 case QIXIS_SYSCLK_133: 102 return 133333333; 103 case QIXIS_SYSCLK_150: 104 return 150000000; 105 case QIXIS_SYSCLK_160: 106 return 160000000; 107 case QIXIS_SYSCLK_166: 108 return 166666666; 109 } 110 return 66666666; 111 } 112 113 int select_i2c_ch_pca9547(u8 ch) 114 { 115 int ret; 116 117 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 118 if (ret) { 119 puts("PCA: failed to select proper channel\n"); 120 return ret; 121 } 122 123 return 0; 124 } 125 126 int config_board_mux(int ctrl_type) 127 { 128 u8 reg5; 129 130 reg5 = QIXIS_READ(brdcfg[5]); 131 132 switch (ctrl_type) { 133 case MUX_TYPE_SDHC: 134 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); 135 break; 136 case MUX_TYPE_DSPI: 137 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); 138 break; 139 default: 140 printf("Wrong mux interface type\n"); 141 return -1; 142 } 143 144 QIXIS_WRITE(brdcfg[5], reg5); 145 146 return 0; 147 } 148 149 int board_init(void) 150 { 151 char *env_hwconfig; 152 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 153 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 154 u32 val; 155 156 init_final_memctl_regs(); 157 158 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); 159 160 env_hwconfig = getenv("hwconfig"); 161 162 if (hwconfig_f("dspi", env_hwconfig) && 163 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) 164 config_board_mux(MUX_TYPE_DSPI); 165 else 166 config_board_mux(MUX_TYPE_SDHC); 167 168 #ifdef CONFIG_ENV_IS_NOWHERE 169 gd->env_addr = (ulong)&default_environment[0]; 170 #endif 171 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 172 173 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); 174 175 /* invert AQR405 IRQ pins polarity */ 176 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); 177 178 return 0; 179 } 180 181 int board_early_init_f(void) 182 { 183 fsl_lsch3_early_init_f(); 184 return 0; 185 } 186 187 int misc_init_r(void) 188 { 189 if (hwconfig("sdhc")) 190 config_board_mux(MUX_TYPE_SDHC); 191 192 return 0; 193 } 194 195 void detail_board_ddr_info(void) 196 { 197 puts("\nDDR "); 198 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 199 print_ddr_info(0); 200 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 201 if (gd->bd->bi_dram[2].size) { 202 puts("\nDP-DDR "); 203 print_size(gd->bd->bi_dram[2].size, ""); 204 print_ddr_info(CONFIG_DP_DDR_CTRL); 205 } 206 #endif 207 } 208 209 int dram_init(void) 210 { 211 gd->ram_size = initdram(0); 212 213 return 0; 214 } 215 216 #if defined(CONFIG_ARCH_MISC_INIT) 217 int arch_misc_init(void) 218 { 219 #ifdef CONFIG_FSL_DEBUG_SERVER 220 debug_server_init(); 221 #endif 222 #ifdef CONFIG_FSL_CAAM 223 sec_init(); 224 #endif 225 return 0; 226 } 227 #endif 228 229 #ifdef CONFIG_FSL_MC_ENET 230 void fdt_fixup_board_enet(void *fdt) 231 { 232 int offset; 233 234 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 235 236 if (offset < 0) 237 offset = fdt_path_offset(fdt, "/fsl-mc"); 238 239 if (offset < 0) { 240 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 241 __func__, offset); 242 return; 243 } 244 245 if (get_mc_boot_status() == 0) 246 fdt_status_okay(fdt, offset); 247 else 248 fdt_status_fail(fdt, offset); 249 } 250 #endif 251 252 #ifdef CONFIG_OF_BOARD_SETUP 253 int ft_board_setup(void *blob, bd_t *bd) 254 { 255 int err; 256 u64 base[CONFIG_NR_DRAM_BANKS]; 257 u64 size[CONFIG_NR_DRAM_BANKS]; 258 259 ft_cpu_setup(blob, bd); 260 261 /* fixup DT for the two GPP DDR banks */ 262 base[0] = gd->bd->bi_dram[0].start; 263 size[0] = gd->bd->bi_dram[0].size; 264 base[1] = gd->bd->bi_dram[1].start; 265 size[1] = gd->bd->bi_dram[1].size; 266 267 fdt_fixup_memory_banks(blob, base, size, 2); 268 269 #ifdef CONFIG_FSL_MC_ENET 270 fdt_fixup_board_enet(blob); 271 err = fsl_mc_ldpaa_exit(bd); 272 if (err) 273 return err; 274 #endif 275 276 return 0; 277 } 278 #endif 279 280 void qixis_dump_switch(void) 281 { 282 int i, nr_of_cfgsw; 283 284 QIXIS_WRITE(cms[0], 0x00); 285 nr_of_cfgsw = QIXIS_READ(cms[1]); 286 287 puts("DIP switch settings dump:\n"); 288 for (i = 1; i <= nr_of_cfgsw; i++) { 289 QIXIS_WRITE(cms[0], i); 290 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 291 } 292 } 293 294 /* 295 * Board rev C and earlier has duplicated I2C addresses for 2nd controller. 296 * Both slots has 0x54, resulting 2nd slot unusable. 297 */ 298 void update_spd_address(unsigned int ctrl_num, 299 unsigned int slot, 300 unsigned int *addr) 301 { 302 u8 sw; 303 304 sw = QIXIS_READ(arch); 305 if ((sw & 0xf) < 0x3) { 306 if (ctrl_num == 1 && slot == 0) 307 *addr = SPD_EEPROM_ADDRESS4; 308 else if (ctrl_num == 1 && slot == 1) 309 *addr = SPD_EEPROM_ADDRESS3; 310 } 311 } 312