1 /* 2 * Copyright (C) 2017 NXP Semiconductors 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <malloc.h> 9 #include <errno.h> 10 #include <netdev.h> 11 #include <fsl_ifc.h> 12 #include <fsl_ddr.h> 13 #include <asm/io.h> 14 #include <hwconfig.h> 15 #include <fdt_support.h> 16 #include <libfdt.h> 17 #include <fsl-mc/fsl_mc.h> 18 #include <environment.h> 19 #include <efi_loader.h> 20 #include <i2c.h> 21 #include <asm/arch/mmu.h> 22 #include <asm/arch/soc.h> 23 #include <asm/arch/ppa.h> 24 #include <fsl_sec.h> 25 26 #include "../common/qixis.h" 27 #include "ls2080ardb_qixis.h" 28 #include "../common/vid.h" 29 30 #define PIN_MUX_SEL_SDHC 0x00 31 #define PIN_MUX_SEL_DSPI 0x0a 32 33 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 34 DECLARE_GLOBAL_DATA_PTR; 35 36 enum { 37 MUX_TYPE_SDHC, 38 MUX_TYPE_DSPI, 39 }; 40 41 unsigned long long get_qixis_addr(void) 42 { 43 unsigned long long addr; 44 45 if (gd->flags & GD_FLG_RELOC) 46 addr = QIXIS_BASE_PHYS; 47 else 48 addr = QIXIS_BASE_PHYS_EARLY; 49 50 /* 51 * IFC address under 256MB is mapped to 0x30000000, any address above 52 * is mapped to 0x5_10000000 up to 4GB. 53 */ 54 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 55 56 return addr; 57 } 58 59 int checkboard(void) 60 { 61 u8 sw; 62 char buf[15]; 63 64 cpu_name(buf); 65 printf("Board: %s-RDB, ", buf); 66 67 sw = QIXIS_READ(arch); 68 printf("Board Arch: V%d, ", sw >> 4); 69 printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 70 71 sw = QIXIS_READ(brdcfg[0]); 72 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 73 74 if (sw < 0x8) 75 printf("vBank: %d\n", sw); 76 else if (sw == 0x9) 77 puts("NAND\n"); 78 else 79 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 80 81 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 82 83 puts("SERDES1 Reference : "); 84 printf("Clock1 = 156.25MHz "); 85 printf("Clock2 = 156.25MHz"); 86 87 puts("\nSERDES2 Reference : "); 88 printf("Clock1 = 100MHz "); 89 printf("Clock2 = 100MHz\n"); 90 91 return 0; 92 } 93 94 unsigned long get_board_sys_clk(void) 95 { 96 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 97 98 switch (sysclk_conf & 0x0F) { 99 case QIXIS_SYSCLK_83: 100 return 83333333; 101 case QIXIS_SYSCLK_100: 102 return 100000000; 103 case QIXIS_SYSCLK_125: 104 return 125000000; 105 case QIXIS_SYSCLK_133: 106 return 133333333; 107 case QIXIS_SYSCLK_150: 108 return 150000000; 109 case QIXIS_SYSCLK_160: 110 return 160000000; 111 case QIXIS_SYSCLK_166: 112 return 166666666; 113 } 114 return 66666666; 115 } 116 117 int select_i2c_ch_pca9547(u8 ch) 118 { 119 int ret; 120 121 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 122 if (ret) { 123 puts("PCA: failed to select proper channel\n"); 124 return ret; 125 } 126 127 return 0; 128 } 129 130 int i2c_multiplexer_select_vid_channel(u8 channel) 131 { 132 return select_i2c_ch_pca9547(channel); 133 } 134 135 int config_board_mux(int ctrl_type) 136 { 137 u8 reg5; 138 139 reg5 = QIXIS_READ(brdcfg[5]); 140 141 switch (ctrl_type) { 142 case MUX_TYPE_SDHC: 143 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); 144 break; 145 case MUX_TYPE_DSPI: 146 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); 147 break; 148 default: 149 printf("Wrong mux interface type\n"); 150 return -1; 151 } 152 153 QIXIS_WRITE(brdcfg[5], reg5); 154 155 return 0; 156 } 157 158 int board_init(void) 159 { 160 char *env_hwconfig; 161 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 162 #ifdef CONFIG_FSL_MC_ENET 163 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 164 #endif 165 u32 val; 166 167 init_final_memctl_regs(); 168 169 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); 170 171 env_hwconfig = getenv("hwconfig"); 172 173 if (hwconfig_f("dspi", env_hwconfig) && 174 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) 175 config_board_mux(MUX_TYPE_DSPI); 176 else 177 config_board_mux(MUX_TYPE_SDHC); 178 179 #ifdef CONFIG_ENV_IS_NOWHERE 180 gd->env_addr = (ulong)&default_environment[0]; 181 #endif 182 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 183 184 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); 185 186 #ifdef CONFIG_FSL_LS_PPA 187 ppa_init(); 188 #endif 189 190 #ifdef CONFIG_FSL_MC_ENET 191 /* invert AQR405 IRQ pins polarity */ 192 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); 193 #endif 194 #ifdef CONFIG_FSL_CAAM 195 sec_init(); 196 #endif 197 198 return 0; 199 } 200 201 int board_early_init_f(void) 202 { 203 fsl_lsch3_early_init_f(); 204 return 0; 205 } 206 207 int misc_init_r(void) 208 { 209 #ifdef CONFIG_FSL_QIXIS 210 u8 sw; 211 212 sw = QIXIS_READ(arch); 213 /* 214 * LS2080ARDB/LS2088ARDB RevF board has smart voltage translator 215 * which needs to be programmed to enable high speed SD interface 216 * by setting GPIO4_10 output to zero 217 */ 218 if ((sw & 0xf) == 0x5) { 219 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 | 220 in_le32(GPIO4_GPDIR_ADDR))); 221 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) & 222 in_le32(GPIO4_GPDAT_ADDR))); 223 } 224 #endif 225 226 if (hwconfig("sdhc")) 227 config_board_mux(MUX_TYPE_SDHC); 228 229 if (adjust_vdd(0)) 230 printf("Warning: Adjusting core voltage failed.\n"); 231 232 return 0; 233 } 234 235 void detail_board_ddr_info(void) 236 { 237 puts("\nDDR "); 238 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 239 print_ddr_info(0); 240 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 241 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { 242 puts("\nDP-DDR "); 243 print_size(gd->bd->bi_dram[2].size, ""); 244 print_ddr_info(CONFIG_DP_DDR_CTRL); 245 } 246 #endif 247 } 248 249 #if defined(CONFIG_ARCH_MISC_INIT) 250 int arch_misc_init(void) 251 { 252 return 0; 253 } 254 #endif 255 256 #ifdef CONFIG_FSL_MC_ENET 257 void fdt_fixup_board_enet(void *fdt) 258 { 259 int offset; 260 261 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 262 263 if (offset < 0) 264 offset = fdt_path_offset(fdt, "/fsl-mc"); 265 266 if (offset < 0) { 267 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 268 __func__, offset); 269 return; 270 } 271 272 if (get_mc_boot_status() == 0) 273 fdt_status_okay(fdt, offset); 274 else 275 fdt_status_fail(fdt, offset); 276 } 277 278 void board_quiesce_devices(void) 279 { 280 fsl_mc_ldpaa_exit(gd->bd); 281 } 282 #endif 283 284 #ifdef CONFIG_OF_BOARD_SETUP 285 int ft_board_setup(void *blob, bd_t *bd) 286 { 287 u64 base[CONFIG_NR_DRAM_BANKS]; 288 u64 size[CONFIG_NR_DRAM_BANKS]; 289 290 ft_cpu_setup(blob, bd); 291 292 /* fixup DT for the two GPP DDR banks */ 293 base[0] = gd->bd->bi_dram[0].start; 294 size[0] = gd->bd->bi_dram[0].size; 295 base[1] = gd->bd->bi_dram[1].start; 296 size[1] = gd->bd->bi_dram[1].size; 297 298 #ifdef CONFIG_RESV_RAM 299 /* reduce size if reserved memory is within this bank */ 300 if (gd->arch.resv_ram >= base[0] && 301 gd->arch.resv_ram < base[0] + size[0]) 302 size[0] = gd->arch.resv_ram - base[0]; 303 else if (gd->arch.resv_ram >= base[1] && 304 gd->arch.resv_ram < base[1] + size[1]) 305 size[1] = gd->arch.resv_ram - base[1]; 306 #endif 307 308 fdt_fixup_memory_banks(blob, base, size, 2); 309 310 fsl_fdt_fixup_dr_usb(blob, bd); 311 312 #ifdef CONFIG_FSL_MC_ENET 313 fdt_fixup_board_enet(blob); 314 #endif 315 316 return 0; 317 } 318 #endif 319 320 void qixis_dump_switch(void) 321 { 322 int i, nr_of_cfgsw; 323 324 QIXIS_WRITE(cms[0], 0x00); 325 nr_of_cfgsw = QIXIS_READ(cms[1]); 326 327 puts("DIP switch settings dump:\n"); 328 for (i = 1; i <= nr_of_cfgsw; i++) { 329 QIXIS_WRITE(cms[0], i); 330 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 331 } 332 } 333 334 /* 335 * Board rev C and earlier has duplicated I2C addresses for 2nd controller. 336 * Both slots has 0x54, resulting 2nd slot unusable. 337 */ 338 void update_spd_address(unsigned int ctrl_num, 339 unsigned int slot, 340 unsigned int *addr) 341 { 342 u8 sw; 343 344 sw = QIXIS_READ(arch); 345 if ((sw & 0xf) < 0x3) { 346 if (ctrl_num == 1 && slot == 0) 347 *addr = SPD_EEPROM_ADDRESS4; 348 else if (ctrl_num == 1 && slot == 1) 349 *addr = SPD_EEPROM_ADDRESS3; 350 } 351 } 352