1Overview 2-------- 3The LS2080A Development System (QDS) is a high-performance computing, 4evaluation, and development platform that supports the QorIQ LS2080A 5and LS2088A Layerscape Architecture processor. The LS2080AQDS provides 6validation and SW development platform for the Freescale LS2080A, LS2088A 7processor series, with a complete debugging environment. 8 9LS2080A, LS2088A SoC Overview 10-------------------- 11Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A, 12LS2088A SoC overview. 13 14 LS2080AQDS board Overview 15 ----------------------- 16 - SERDES Connections, 16 lanes supporting: 17 - PCI Express - 3.0 18 - SGMII, SGMII 2.5 19 - QSGMII 20 - SATA 3.0 21 - XAUI 22 - XFI 23 - DDR Controller 24 - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four 25 chip-selects and two DIMM connectors. Support is up to 2133MT/s. 26 - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects 27 and two DIMM connectors. Support is up to 1600MT/s. 28 -IFC/Local Bus 29 - IFC rev. 2.0 implementation supporting Little Endian connection scheme. 30 - One in-socket 128 MB NOR flash 16-bit data bus 31 - One 512 MB NAND flash with ECC support 32 - IFC Test Port 33 - PromJet Port 34 - FPGA connection 35 - USB 3.0 36 - Two high speed USB 3.0 ports 37 - First USB 3.0 port configured as Host with Type-A connector 38 - Second USB 3.0 port configured as OTG with micro-AB connector 39 - SDHC: PCIe x1 Right Angle connector for supporting following cards 40 - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only 41 - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only 42 - 4-bit eMMC Card Rev 4.4 (1.8V only) 43 - 8-bit eMMC Card Rev 4.5 (1.8V only) 44 - SD Card Rev 2.0 and Rev 3.0 45 - DSPI: 3 high-speed flash Memory for storage 46 - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) 47 - 8 MB high-speed flash Memory (up to 104 MHz) 48 - 512 MB low-speed flash Memory (up to 40 MHz) 49 - QSPI: via NAND/QSPI Card 50 - 4 I2C controllers 51 - Two SATA onboard connectors 52 - UART 53 - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s 54 - Two DB9 D-Type connectors supporting one Serial port each 55 - ARM JTAG support 56 57Memory map from core's view 58---------------------------- 590x00_0000_0000 .. 0x00_000F_FFFF Boot Rom 600x00_0100_0000 .. 0x00_0FFF_FFFF CCSR 610x00_1800_0000 .. 0x00_181F_FFFF OCRAM 620x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 630x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 640x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 650x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 66 67Other addresses are either reserved, or not used directly by U-Boot. 68This list should be updated when more addresses are used. 69 70IFC region map from core's view 71------------------------------- 72During boot i.e. IFC Region #1:- 73 0x30000000 - 0x37ffffff : 128MB : NOR flash 74 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 75 0x3C000000 - 0x40000000 : 64MB : FPGA etc 76 77After relocate to DDR i.e. IFC Region #2:- 78 0x5_1000_0000..0x5_1fff_ffff Memory Hole 79 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 80 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 81 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 82 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 83 84Booting Options 85--------------- 86a) Promjet Boot 87b) NOR boot 88c) NAND boot 89d) SD boot 90e) QSPI boot 91 92Memory map for NOR boot 93------------------------- 94Image Flash Offset 95RCW+PBI 0x00000000 96Boot firmware (U-Boot) 0x00100000 97Boot firmware Environment 0x00300000 98PPA firmware 0x00400000 99DPAA2 MC 0x00A00000 100DPAA2 DPL 0x00D00000 101DPAA2 DPC 0x00E00000 102Kernel.itb 0x01000000 103 104Environment Variables 105--------------------- 106- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined 107 the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. 108 109- mcmemsize: MC DRAM block size. If this variable is not defined 110 the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. 111 112Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) 113------------------------------------------------------------------- 114One needs to use appropriate bootargs to boot Linux flavors which do 115not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown 116below: 117 118=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram 119 earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m 120 hugepages=16 mem=2048M' 121 122 123X-QSGMII-16PORT riser card 124---------------------------- 125The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes 126interfaces implemented in PCIe form factor board. 127It supports following: 128 - Card can operate with up to 4 QSGMII lane simultaneously 129 - Card can operate with up to 8 SGMII lane simultaneously 130 131Supported card configuration 132 - CSEL : ON ON ON ON 133 - MSEL1 : ON ON ON ON OFF OFF OFF OFF 134 - MSEL2 : OFF OFF OFF OFF ON ON ON ON 135 136To enable this card: modify hwconfig to add "xqsgmii" variable. 137 138Supported PHY addresses during SGMII: 139#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 140#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 141#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 142#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 143#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 144#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 145#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 146#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 147 148Mapping DPMACx to PHY during SGMII 149DPMAC1 -> PHY1-P0 150DPMAC2 -> PHY2-P0 151DPMAC3 -> PHY3-P0 152DPMAC4 -> PHY4-P0 153DPMAC5 -> PHY3-P2 154DPMAC6 -> PHY1-P2 155DPMAC7 -> PHY4-P1 156DPMAC8 -> PHY2-P2 157DPMAC9 -> PHY1-P0 158DPMAC10 -> PHY2-P0 159DPMAC11 -> PHY3-P0 160DPMAC12 -> PHY4-P0 161DPMAC13 -> PHY3-P2 162DPMAC14 -> PHY1-P2 163DPMAC15 -> PHY4-P1 164DPMAC16 -> PHY2-P2 165 166 167Supported PHY address during QSGMII 168#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 169#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 170#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 171#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 172#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 173#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 174#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 175#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 176#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 177#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 178#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 179#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 180#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 181#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 182#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 183#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 184 185Mapping DPMACx to PHY during QSGMII 186DPMAC1 -> PHY1-P3 187DPMAC2 -> PHY1-P2 188DPMAC3 -> PHY1-P1 189DPMAC4 -> PHY1-P0 190DPMAC5 -> PHY2-P3 191DPMAC6 -> PHY2-P2 192DPMAC7 -> PHY2-P1 193DPMAC8 -> PHY2-P0 194DPMAC9 -> PHY3-P0 195DPMAC10 -> PHY3-P1 196DPMAC11 -> PHY3-P2 197DPMAC12 -> PHY3-P3 198DPMAC13 -> PHY4-P0 199DPMAC14 -> PHY4-P1 200DPMAC15 -> PHY4-P2 201DPMAC16 -> PHY4-P3 202 203