1*126fe70dSShaohui Xie /* 2*126fe70dSShaohui Xie * Copyright 2016 Freescale Semiconductor, Inc. 3*126fe70dSShaohui Xie * 4*126fe70dSShaohui Xie * SPDX-License-Identifier: GPL-2.0+ 5*126fe70dSShaohui Xie */ 6*126fe70dSShaohui Xie 7*126fe70dSShaohui Xie #ifndef __DDR_H__ 8*126fe70dSShaohui Xie #define __DDR_H__ 9*126fe70dSShaohui Xie 10*126fe70dSShaohui Xie void erratum_a008850_post(void); 11*126fe70dSShaohui Xie 12*126fe70dSShaohui Xie struct board_specific_parameters { 13*126fe70dSShaohui Xie u32 n_ranks; 14*126fe70dSShaohui Xie u32 datarate_mhz_high; 15*126fe70dSShaohui Xie u32 rank_gb; 16*126fe70dSShaohui Xie u32 clk_adjust; 17*126fe70dSShaohui Xie u32 wrlvl_start; 18*126fe70dSShaohui Xie u32 wrlvl_ctl_2; 19*126fe70dSShaohui Xie u32 wrlvl_ctl_3; 20*126fe70dSShaohui Xie }; 21*126fe70dSShaohui Xie 22*126fe70dSShaohui Xie /* 23*126fe70dSShaohui Xie * These tables contain all valid speeds we want to override with board 24*126fe70dSShaohui Xie * specific parameters. datarate_mhz_high values need to be in ascending order 25*126fe70dSShaohui Xie * for each n_ranks group. 26*126fe70dSShaohui Xie */ 27*126fe70dSShaohui Xie static const struct board_specific_parameters udimm0[] = { 28*126fe70dSShaohui Xie /* 29*126fe70dSShaohui Xie * memory controller 0 30*126fe70dSShaohui Xie * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 31*126fe70dSShaohui Xie * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 32*126fe70dSShaohui Xie */ 33*126fe70dSShaohui Xie {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, 34*126fe70dSShaohui Xie {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, 35*126fe70dSShaohui Xie {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, 36*126fe70dSShaohui Xie {2, 2300, 0, 8, 9, 0x0A0C0D11, 0x1214150E,}, 37*126fe70dSShaohui Xie {} 38*126fe70dSShaohui Xie }; 39*126fe70dSShaohui Xie 40*126fe70dSShaohui Xie static const struct board_specific_parameters *udimms[] = { 41*126fe70dSShaohui Xie udimm0, 42*126fe70dSShaohui Xie }; 43*126fe70dSShaohui Xie 44*126fe70dSShaohui Xie #endif 45