1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <hwconfig.h> 14 #include <ahci.h> 15 #include <mmc.h> 16 #include <scsi.h> 17 #include <fm_eth.h> 18 #include <fsl_csu.h> 19 #include <fsl_esdhc.h> 20 #include <fsl_ifc.h> 21 #include <environment.h> 22 #include <fsl_sec.h> 23 #include "cpld.h" 24 #ifdef CONFIG_U_QE 25 #include <fsl_qe.h> 26 #endif 27 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 int checkboard(void) 32 { 33 static const char *freq[3] = {"100.00MHZ", "156.25MHZ"}; 34 #ifndef CONFIG_SD_BOOT 35 u8 cfg_rcw_src1, cfg_rcw_src2; 36 u32 cfg_rcw_src; 37 #endif 38 u32 sd1refclk_sel; 39 40 printf("Board: LS1043ARDB, boot from "); 41 42 #ifdef CONFIG_SD_BOOT 43 puts("SD\n"); 44 #else 45 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 46 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 47 cpld_rev_bit(&cfg_rcw_src1); 48 cfg_rcw_src = cfg_rcw_src1; 49 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 50 51 if (cfg_rcw_src == 0x25) 52 printf("vBank %d\n", CPLD_READ(vbank)); 53 else if (cfg_rcw_src == 0x106) 54 puts("NAND\n"); 55 else 56 printf("Invalid setting of SW4\n"); 57 #endif 58 59 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 60 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 61 62 puts("SERDES Reference Clocks:\n"); 63 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 64 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 65 66 return 0; 67 } 68 69 int dram_init(void) 70 { 71 gd->ram_size = initdram(0); 72 73 return 0; 74 } 75 76 int board_early_init_f(void) 77 { 78 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 79 u32 usb_pwrfault; 80 81 fsl_lsch2_early_init_f(); 82 83 #ifdef CONFIG_HAS_FSL_XHCI_USB 84 out_be32(&scfg->rcwpmuxcr0, 0x3333); 85 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 86 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 87 SCFG_USBPWRFAULT_USB3_SHIFT) | 88 (SCFG_USBPWRFAULT_DEDICATED << 89 SCFG_USBPWRFAULT_USB2_SHIFT) | 90 (SCFG_USBPWRFAULT_SHARED << 91 SCFG_USBPWRFAULT_USB1_SHIFT); 92 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 93 #endif 94 95 return 0; 96 } 97 98 int board_init(void) 99 { 100 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 101 102 /* 103 * Set CCI-400 control override register to enable barrier 104 * transaction 105 */ 106 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 107 108 #ifdef CONFIG_FSL_IFC 109 init_final_memctl_regs(); 110 #endif 111 112 #ifdef CONFIG_ENV_IS_NOWHERE 113 gd->env_addr = (ulong)&default_environment[0]; 114 #endif 115 116 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 117 enable_layerscape_ns_access(); 118 #endif 119 120 #ifdef CONFIG_U_QE 121 u_qe_init(); 122 #endif 123 124 return 0; 125 } 126 127 int config_board_mux(void) 128 { 129 return 0; 130 } 131 132 #if defined(CONFIG_MISC_INIT_R) 133 int misc_init_r(void) 134 { 135 config_board_mux(); 136 #ifdef CONFIG_SECURE_BOOT 137 /* In case of Secure Boot, the IBR configures the SMMU 138 * to allow only Secure transactions. 139 * SMMU must be reset in bypass mode. 140 * Set the ClientPD bit and Clear the USFCFG Bit 141 */ 142 u32 val; 143 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 144 out_le32(SMMU_SCR0, val); 145 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 146 out_le32(SMMU_NSCR0, val); 147 #endif 148 #ifdef CONFIG_FSL_CAAM 149 return sec_init(); 150 #endif 151 return 0; 152 } 153 #endif 154 155 int ft_board_setup(void *blob, bd_t *bd) 156 { 157 u64 base[CONFIG_NR_DRAM_BANKS]; 158 u64 size[CONFIG_NR_DRAM_BANKS]; 159 160 /* fixup DT for the two DDR banks */ 161 base[0] = gd->bd->bi_dram[0].start; 162 size[0] = gd->bd->bi_dram[0].size; 163 base[1] = gd->bd->bi_dram[1].start; 164 size[1] = gd->bd->bi_dram[1].size; 165 166 fdt_fixup_memory_banks(blob, base, size, 2); 167 ft_cpu_setup(blob, bd); 168 169 #ifdef CONFIG_SYS_DPAA_FMAN 170 fdt_fixup_fman_ethernet(blob); 171 #endif 172 return 0; 173 } 174 175 u8 flash_read8(void *addr) 176 { 177 return __raw_readb(addr + 1); 178 } 179 180 void flash_write16(u16 val, void *addr) 181 { 182 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 183 184 __raw_writew(shftval, addr); 185 } 186 187 u16 flash_read16(void *addr) 188 { 189 u16 val = __raw_readw(addr); 190 191 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 192 } 193