1*e8297341SShaohui Xie /*
2*e8297341SShaohui Xie * Copyright 2015 Freescale Semiconductor, Inc.
3*e8297341SShaohui Xie *
4*e8297341SShaohui Xie * SPDX-License-Identifier: GPL-2.0+
5*e8297341SShaohui Xie */
6*e8297341SShaohui Xie #include <common.h>
7*e8297341SShaohui Xie #include <asm/io.h>
8*e8297341SShaohui Xie #include <netdev.h>
9*e8297341SShaohui Xie #include <fm_eth.h>
10*e8297341SShaohui Xie #include <fsl_dtsec.h>
11*e8297341SShaohui Xie #include <fsl_mdio.h>
12*e8297341SShaohui Xie #include <malloc.h>
13*e8297341SShaohui Xie
14*e8297341SShaohui Xie #include "../common/fman.h"
15*e8297341SShaohui Xie
board_eth_init(bd_t * bis)16*e8297341SShaohui Xie int board_eth_init(bd_t *bis)
17*e8297341SShaohui Xie {
18*e8297341SShaohui Xie #ifdef CONFIG_FMAN_ENET
19*e8297341SShaohui Xie int i;
20*e8297341SShaohui Xie struct memac_mdio_info dtsec_mdio_info;
21*e8297341SShaohui Xie struct memac_mdio_info tgec_mdio_info;
22*e8297341SShaohui Xie struct mii_dev *dev;
23*e8297341SShaohui Xie u32 srds_s1;
24*e8297341SShaohui Xie struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
25*e8297341SShaohui Xie
26*e8297341SShaohui Xie srds_s1 = in_be32(&gur->rcwsr[4]) &
27*e8297341SShaohui Xie FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
28*e8297341SShaohui Xie srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
29*e8297341SShaohui Xie
30*e8297341SShaohui Xie dtsec_mdio_info.regs =
31*e8297341SShaohui Xie (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
32*e8297341SShaohui Xie
33*e8297341SShaohui Xie dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
34*e8297341SShaohui Xie
35*e8297341SShaohui Xie /* Register the 1G MDIO bus */
36*e8297341SShaohui Xie fm_memac_mdio_init(bis, &dtsec_mdio_info);
37*e8297341SShaohui Xie
38*e8297341SShaohui Xie tgec_mdio_info.regs =
39*e8297341SShaohui Xie (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
40*e8297341SShaohui Xie tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
41*e8297341SShaohui Xie
42*e8297341SShaohui Xie /* Register the 10G MDIO bus */
43*e8297341SShaohui Xie fm_memac_mdio_init(bis, &tgec_mdio_info);
44*e8297341SShaohui Xie
45*e8297341SShaohui Xie /* Set the two on-board RGMII PHY address */
46*e8297341SShaohui Xie fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
47*e8297341SShaohui Xie fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
48*e8297341SShaohui Xie
49*e8297341SShaohui Xie /* QSGMII on lane B, MAC 1/2/5/6 */
50*e8297341SShaohui Xie fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);
51*e8297341SShaohui Xie fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);
52*e8297341SShaohui Xie fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);
53*e8297341SShaohui Xie fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);
54*e8297341SShaohui Xie
55*e8297341SShaohui Xie switch (srds_s1) {
56*e8297341SShaohui Xie case 0x1455:
57*e8297341SShaohui Xie break;
58*e8297341SShaohui Xie default:
59*e8297341SShaohui Xie printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n",
60*e8297341SShaohui Xie srds_s1);
61*e8297341SShaohui Xie break;
62*e8297341SShaohui Xie }
63*e8297341SShaohui Xie
64*e8297341SShaohui Xie dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
65*e8297341SShaohui Xie for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
66*e8297341SShaohui Xie fm_info_set_mdio(i, dev);
67*e8297341SShaohui Xie
68*e8297341SShaohui Xie /* XFI on lane A, MAC 9 */
69*e8297341SShaohui Xie fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
70*e8297341SShaohui Xie dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
71*e8297341SShaohui Xie fm_info_set_mdio(FM1_10GEC1, dev);
72*e8297341SShaohui Xie
73*e8297341SShaohui Xie cpu_eth_init(bis);
74*e8297341SShaohui Xie #endif
75*e8297341SShaohui Xie
76*e8297341SShaohui Xie return pci_eth_init(bis);
77*e8297341SShaohui Xie }
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