1*f3a8e2b7SMingkai Hu /* 2*f3a8e2b7SMingkai Hu * Copyright 2015 Freescale Semiconductor 3*f3a8e2b7SMingkai Hu * 4*f3a8e2b7SMingkai Hu * SPDX-License-Identifier: GPL-2.0+ 5*f3a8e2b7SMingkai Hu * 6*f3a8e2b7SMingkai Hu * Freescale LS1043ARDB board-specific CPLD controlling supports. 7*f3a8e2b7SMingkai Hu */ 8*f3a8e2b7SMingkai Hu 9*f3a8e2b7SMingkai Hu #include <common.h> 10*f3a8e2b7SMingkai Hu #include <command.h> 11*f3a8e2b7SMingkai Hu #include <asm/io.h> 12*f3a8e2b7SMingkai Hu #include "cpld.h" 13*f3a8e2b7SMingkai Hu 14*f3a8e2b7SMingkai Hu u8 cpld_read(unsigned int reg) 15*f3a8e2b7SMingkai Hu { 16*f3a8e2b7SMingkai Hu void *p = (void *)CONFIG_SYS_CPLD_BASE; 17*f3a8e2b7SMingkai Hu 18*f3a8e2b7SMingkai Hu return in_8(p + reg); 19*f3a8e2b7SMingkai Hu } 20*f3a8e2b7SMingkai Hu 21*f3a8e2b7SMingkai Hu void cpld_write(unsigned int reg, u8 value) 22*f3a8e2b7SMingkai Hu { 23*f3a8e2b7SMingkai Hu void *p = (void *)CONFIG_SYS_CPLD_BASE; 24*f3a8e2b7SMingkai Hu 25*f3a8e2b7SMingkai Hu out_8(p + reg, value); 26*f3a8e2b7SMingkai Hu } 27*f3a8e2b7SMingkai Hu 28*f3a8e2b7SMingkai Hu /* Set the boot bank to the alternate bank */ 29*f3a8e2b7SMingkai Hu void cpld_set_altbank(void) 30*f3a8e2b7SMingkai Hu { 31*f3a8e2b7SMingkai Hu u8 reg4 = CPLD_READ(soft_mux_on); 32*f3a8e2b7SMingkai Hu u8 reg7 = CPLD_READ(vbank); 33*f3a8e2b7SMingkai Hu 34*f3a8e2b7SMingkai Hu CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL); 35*f3a8e2b7SMingkai Hu 36*f3a8e2b7SMingkai Hu reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; 37*f3a8e2b7SMingkai Hu CPLD_WRITE(vbank, reg7); 38*f3a8e2b7SMingkai Hu 39*f3a8e2b7SMingkai Hu CPLD_WRITE(system_rst, 1); 40*f3a8e2b7SMingkai Hu } 41*f3a8e2b7SMingkai Hu 42*f3a8e2b7SMingkai Hu /* Set the boot bank to the default bank */ 43*f3a8e2b7SMingkai Hu void cpld_set_defbank(void) 44*f3a8e2b7SMingkai Hu { 45*f3a8e2b7SMingkai Hu CPLD_WRITE(global_rst, 1); 46*f3a8e2b7SMingkai Hu } 47*f3a8e2b7SMingkai Hu 48*f3a8e2b7SMingkai Hu #ifdef DEBUG 49*f3a8e2b7SMingkai Hu static void cpld_dump_regs(void) 50*f3a8e2b7SMingkai Hu { 51*f3a8e2b7SMingkai Hu printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); 52*f3a8e2b7SMingkai Hu printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); 53*f3a8e2b7SMingkai Hu printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); 54*f3a8e2b7SMingkai Hu printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); 55*f3a8e2b7SMingkai Hu printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); 56*f3a8e2b7SMingkai Hu printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); 57*f3a8e2b7SMingkai Hu printf("vbank = %x\n", CPLD_READ(vbank)); 58*f3a8e2b7SMingkai Hu printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); 59*f3a8e2b7SMingkai Hu printf("uart_sel = %x\n", CPLD_READ(uart_sel)); 60*f3a8e2b7SMingkai Hu printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); 61*f3a8e2b7SMingkai Hu printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel)); 62*f3a8e2b7SMingkai Hu printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel)); 63*f3a8e2b7SMingkai Hu printf("status_led = %x\n", CPLD_READ(status_led)); 64*f3a8e2b7SMingkai Hu putc('\n'); 65*f3a8e2b7SMingkai Hu } 66*f3a8e2b7SMingkai Hu #endif 67*f3a8e2b7SMingkai Hu 68*f3a8e2b7SMingkai Hu void cpld_rev_bit(unsigned char *value) 69*f3a8e2b7SMingkai Hu { 70*f3a8e2b7SMingkai Hu u8 rev_val, val; 71*f3a8e2b7SMingkai Hu int i; 72*f3a8e2b7SMingkai Hu 73*f3a8e2b7SMingkai Hu val = *value; 74*f3a8e2b7SMingkai Hu rev_val = val & 1; 75*f3a8e2b7SMingkai Hu for (i = 1; i <= 7; i++) { 76*f3a8e2b7SMingkai Hu val >>= 1; 77*f3a8e2b7SMingkai Hu rev_val <<= 1; 78*f3a8e2b7SMingkai Hu rev_val |= val & 1; 79*f3a8e2b7SMingkai Hu } 80*f3a8e2b7SMingkai Hu 81*f3a8e2b7SMingkai Hu *value = rev_val; 82*f3a8e2b7SMingkai Hu } 83*f3a8e2b7SMingkai Hu 84*f3a8e2b7SMingkai Hu int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 85*f3a8e2b7SMingkai Hu { 86*f3a8e2b7SMingkai Hu int rc = 0; 87*f3a8e2b7SMingkai Hu 88*f3a8e2b7SMingkai Hu if (argc <= 1) 89*f3a8e2b7SMingkai Hu return cmd_usage(cmdtp); 90*f3a8e2b7SMingkai Hu 91*f3a8e2b7SMingkai Hu if (strcmp(argv[1], "reset") == 0) { 92*f3a8e2b7SMingkai Hu if (strcmp(argv[2], "altbank") == 0) 93*f3a8e2b7SMingkai Hu cpld_set_altbank(); 94*f3a8e2b7SMingkai Hu else 95*f3a8e2b7SMingkai Hu cpld_set_defbank(); 96*f3a8e2b7SMingkai Hu #ifdef DEBUG 97*f3a8e2b7SMingkai Hu } else if (strcmp(argv[1], "dump") == 0) { 98*f3a8e2b7SMingkai Hu cpld_dump_regs(); 99*f3a8e2b7SMingkai Hu #endif 100*f3a8e2b7SMingkai Hu } else { 101*f3a8e2b7SMingkai Hu rc = cmd_usage(cmdtp); 102*f3a8e2b7SMingkai Hu } 103*f3a8e2b7SMingkai Hu 104*f3a8e2b7SMingkai Hu return rc; 105*f3a8e2b7SMingkai Hu } 106*f3a8e2b7SMingkai Hu 107*f3a8e2b7SMingkai Hu U_BOOT_CMD( 108*f3a8e2b7SMingkai Hu cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, 109*f3a8e2b7SMingkai Hu "Reset the board or alternate bank", 110*f3a8e2b7SMingkai Hu "reset: reset to default bank\n" 111*f3a8e2b7SMingkai Hu "cpld reset altbank: reset to alternate bank\n" 112*f3a8e2b7SMingkai Hu #ifdef DEBUG 113*f3a8e2b7SMingkai Hu "cpld dump - display the CPLD registers\n" 114*f3a8e2b7SMingkai Hu #endif 115*f3a8e2b7SMingkai Hu ); 116