102b5d2edSShaohui Xie /* 202b5d2edSShaohui Xie * Copyright 2015 Freescale Semiconductor, Inc. 302b5d2edSShaohui Xie * 402b5d2edSShaohui Xie * SPDX-License-Identifier: GPL-2.0+ 502b5d2edSShaohui Xie */ 602b5d2edSShaohui Xie 702b5d2edSShaohui Xie #ifndef __DDR_H__ 802b5d2edSShaohui Xie #define __DDR_H__ 902b5d2edSShaohui Xie 10074596c0SShengzhou Liu extern void erratum_a008850_post(void); 11074596c0SShengzhou Liu 1202b5d2edSShaohui Xie struct board_specific_parameters { 1302b5d2edSShaohui Xie u32 n_ranks; 1402b5d2edSShaohui Xie u32 datarate_mhz_high; 1502b5d2edSShaohui Xie u32 rank_gb; 1602b5d2edSShaohui Xie u32 clk_adjust; 1702b5d2edSShaohui Xie u32 wrlvl_start; 1802b5d2edSShaohui Xie u32 wrlvl_ctl_2; 1902b5d2edSShaohui Xie u32 wrlvl_ctl_3; 2002b5d2edSShaohui Xie u32 cpo_override; 2102b5d2edSShaohui Xie u32 write_data_delay; 2202b5d2edSShaohui Xie u32 force_2t; 2302b5d2edSShaohui Xie }; 2402b5d2edSShaohui Xie 2502b5d2edSShaohui Xie /* 2602b5d2edSShaohui Xie * These tables contain all valid speeds we want to override with board 2702b5d2edSShaohui Xie * specific parameters. datarate_mhz_high values need to be in ascending order 2802b5d2edSShaohui Xie * for each n_ranks group. 2902b5d2edSShaohui Xie */ 3002b5d2edSShaohui Xie static const struct board_specific_parameters udimm0[] = { 3102b5d2edSShaohui Xie /* 3202b5d2edSShaohui Xie * memory controller 0 3302b5d2edSShaohui Xie * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 3402b5d2edSShaohui Xie * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | 3502b5d2edSShaohui Xie */ 3602b5d2edSShaohui Xie #ifdef CONFIG_SYS_FSL_DDR4 37*e04f9d0cSShengzhou Liu {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 38*e04f9d0cSShengzhou Liu {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, 39*e04f9d0cSShengzhou Liu {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,}, 40*e04f9d0cSShengzhou Liu {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, 41*e04f9d0cSShengzhou Liu {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, 4202b5d2edSShaohui Xie #elif defined(CONFIG_SYS_FSL_DDR3) 43*e04f9d0cSShengzhou Liu {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 44*e04f9d0cSShengzhou Liu {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 45*e04f9d0cSShengzhou Liu {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 46*e04f9d0cSShengzhou Liu {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 47*e04f9d0cSShengzhou Liu {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, 48*e04f9d0cSShengzhou Liu {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 49*e04f9d0cSShengzhou Liu {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, 50*e04f9d0cSShengzhou Liu {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, 51*e04f9d0cSShengzhou Liu {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, 5202b5d2edSShaohui Xie #else 5302b5d2edSShaohui Xie #error DDR type not defined 5402b5d2edSShaohui Xie #endif 5502b5d2edSShaohui Xie {} 5602b5d2edSShaohui Xie }; 5702b5d2edSShaohui Xie 5802b5d2edSShaohui Xie static const struct board_specific_parameters *udimms[] = { 5902b5d2edSShaohui Xie udimm0, 6002b5d2edSShaohui Xie }; 6102b5d2edSShaohui Xie 6202b5d2edSShaohui Xie #endif 63