1*dd04832dSXiubo Li /*
2*dd04832dSXiubo Li * Copyright 2014 Freescale Semiconductor, Inc.
3*dd04832dSXiubo Li *
4*dd04832dSXiubo Li * FSL DCU Framebuffer driver
5*dd04832dSXiubo Li *
6*dd04832dSXiubo Li * SPDX-License-Identifier: GPL-2.0+
7*dd04832dSXiubo Li */
8*dd04832dSXiubo Li
9*dd04832dSXiubo Li #include <asm/io.h>
10*dd04832dSXiubo Li #include <common.h>
11*dd04832dSXiubo Li #include <fsl_dcu_fb.h>
12*dd04832dSXiubo Li #include <i2c.h>
13*dd04832dSXiubo Li #include "div64.h"
14*dd04832dSXiubo Li #include "../common/diu_ch7301.h"
15*dd04832dSXiubo Li #include "ls1021aqds_qixis.h"
16*dd04832dSXiubo Li
17*dd04832dSXiubo Li DECLARE_GLOBAL_DATA_PTR;
18*dd04832dSXiubo Li
select_i2c_ch_pca9547(u8 ch)19*dd04832dSXiubo Li static int select_i2c_ch_pca9547(u8 ch)
20*dd04832dSXiubo Li {
21*dd04832dSXiubo Li int ret;
22*dd04832dSXiubo Li
23*dd04832dSXiubo Li ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
24*dd04832dSXiubo Li if (ret) {
25*dd04832dSXiubo Li puts("PCA: failed to select proper channel\n");
26*dd04832dSXiubo Li return ret;
27*dd04832dSXiubo Li }
28*dd04832dSXiubo Li
29*dd04832dSXiubo Li return 0;
30*dd04832dSXiubo Li }
31*dd04832dSXiubo Li
dcu_set_pixel_clock(unsigned int pixclock)32*dd04832dSXiubo Li unsigned int dcu_set_pixel_clock(unsigned int pixclock)
33*dd04832dSXiubo Li {
34*dd04832dSXiubo Li unsigned long long div;
35*dd04832dSXiubo Li
36*dd04832dSXiubo Li div = (unsigned long long)(gd->bus_clk / 1000);
37*dd04832dSXiubo Li div *= (unsigned long long)pixclock;
38*dd04832dSXiubo Li do_div(div, 1000000000);
39*dd04832dSXiubo Li
40*dd04832dSXiubo Li return div;
41*dd04832dSXiubo Li }
42*dd04832dSXiubo Li
platform_dcu_init(unsigned int xres,unsigned int yres,const char * port,struct fb_videomode * dcu_fb_videomode)43*dd04832dSXiubo Li int platform_dcu_init(unsigned int xres, unsigned int yres,
44*dd04832dSXiubo Li const char *port,
45*dd04832dSXiubo Li struct fb_videomode *dcu_fb_videomode)
46*dd04832dSXiubo Li {
47*dd04832dSXiubo Li const char *name;
48*dd04832dSXiubo Li unsigned int pixel_format;
49*dd04832dSXiubo Li int ret;
50*dd04832dSXiubo Li u8 ch;
51*dd04832dSXiubo Li
52*dd04832dSXiubo Li /* Mux I2C3+I2C4 as HSYNC+VSYNC */
53*dd04832dSXiubo Li ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
54*dd04832dSXiubo Li 1, &ch, 1);
55*dd04832dSXiubo Li if (ret) {
56*dd04832dSXiubo Li printf("Error: failed to read I2C @%02x\n",
57*dd04832dSXiubo Li CONFIG_SYS_I2C_QIXIS_ADDR);
58*dd04832dSXiubo Li return ret;
59*dd04832dSXiubo Li }
60*dd04832dSXiubo Li ch &= 0x1F;
61*dd04832dSXiubo Li ch |= 0xA0;
62*dd04832dSXiubo Li ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
63*dd04832dSXiubo Li 1, &ch, 1);
64*dd04832dSXiubo Li if (ret) {
65*dd04832dSXiubo Li printf("Error: failed to write I2C @%02x\n",
66*dd04832dSXiubo Li CONFIG_SYS_I2C_QIXIS_ADDR);
67*dd04832dSXiubo Li return ret;
68*dd04832dSXiubo Li }
69*dd04832dSXiubo Li
70*dd04832dSXiubo Li if (strncmp(port, "hdmi", 4) == 0) {
71*dd04832dSXiubo Li unsigned long pixval;
72*dd04832dSXiubo Li
73*dd04832dSXiubo Li name = "HDMI";
74*dd04832dSXiubo Li
75*dd04832dSXiubo Li pixval = 1000000000 / dcu_fb_videomode->pixclock;
76*dd04832dSXiubo Li pixval *= 1000;
77*dd04832dSXiubo Li
78*dd04832dSXiubo Li i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
79*dd04832dSXiubo Li select_i2c_ch_pca9547(I2C_MUX_CH_CH7301);
80*dd04832dSXiubo Li diu_set_dvi_encoder(pixval);
81*dd04832dSXiubo Li select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
82*dd04832dSXiubo Li } else {
83*dd04832dSXiubo Li return 0;
84*dd04832dSXiubo Li }
85*dd04832dSXiubo Li
86*dd04832dSXiubo Li printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
87*dd04832dSXiubo Li
88*dd04832dSXiubo Li pixel_format = 32;
89*dd04832dSXiubo Li fsl_dcu_init(xres, yres, pixel_format);
90*dd04832dSXiubo Li
91*dd04832dSXiubo Li return 0;
92*dd04832dSXiubo Li }
93