1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <hwconfig.h> 14 #include <ahci.h> 15 #include <mmc.h> 16 #include <scsi.h> 17 #include <fsl_esdhc.h> 18 #include <environment.h> 19 #include <fsl_mmdc.h> 20 #include <netdev.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 25 { 26 int timeout = 1000; 27 28 out_be32(ptr, value); 29 30 while (in_be32(ptr) & bits) { 31 udelay(100); 32 timeout--; 33 } 34 if (timeout <= 0) 35 puts("Error: wait for clear timeout.\n"); 36 } 37 38 int checkboard(void) 39 { 40 u8 in1; 41 42 puts("Board: LS1012ARDB "); 43 44 /* Initialize i2c early for Serial flash bank information */ 45 i2c_set_bus_num(0); 46 47 if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) { 48 printf("Error reading i2c boot information!\n"); 49 return 0; /* Don't want to hang() on this error */ 50 } 51 52 puts("Version"); 53 if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A) 54 puts(": RevA"); 55 else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B) 56 puts(": RevB"); 57 else 58 puts(": unknown"); 59 60 printf(", boot from QSPI"); 61 if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU) 62 puts(": emu\n"); 63 else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1) 64 puts(": bank1\n"); 65 else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2) 66 puts(": bank2\n"); 67 else 68 puts("unknown\n"); 69 70 return 0; 71 } 72 73 void mmdc_init(void) 74 { 75 struct mmdc_p_regs *mmdc = 76 (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; 77 78 out_be32(&mmdc->mdscr, CONFIGURATION_REQ); 79 80 /* configure timing parms */ 81 out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); 82 out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); 83 out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); 84 out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); 85 86 /* other parms */ 87 out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); 88 out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); 89 out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); 90 out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); 91 92 /* out of reset delays */ 93 out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); 94 95 /* physical parms */ 96 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); 97 out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); 98 99 /* Enable MMDC */ 100 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); 101 102 /* dram init sequence: update MRs */ 103 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | 104 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); 105 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 106 CMD_BANK_ADDR_3)); 107 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 108 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); 109 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | 110 CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | 111 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); 112 113 /* dram init sequence: ZQCL */ 114 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 115 CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); 116 set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 117 CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, 118 FORCE_ZQ_AUTO_CALIBRATION); 119 120 /* Calibrations now: wr lvl */ 121 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | 122 CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 123 CMD_BANK_ADDR_1)); 124 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); 125 set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); 126 127 mdelay(1); 128 129 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 130 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); 131 out_be32(&mmdc->mdscr, CONFIGURATION_REQ); 132 133 mdelay(1); 134 135 /* Calibrations now: Read DQS gating calibration */ 136 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 137 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); 138 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 139 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); 140 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); 141 out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); 142 set_wait_for_bits_clear(&mmdc->mpdgctrl0, 143 AUTO_RD_DQS_GATING_CALIBRATION_EN, 144 AUTO_RD_DQS_GATING_CALIBRATION_EN); 145 146 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 147 CMD_BANK_ADDR_3)); 148 149 /* Calibrations now: Read calibration */ 150 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 151 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); 152 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 153 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); 154 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); 155 set_wait_for_bits_clear(&mmdc->mprddlhwctl, 156 AUTO_RD_CALIBRATION_EN, 157 AUTO_RD_CALIBRATION_EN); 158 159 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 160 CMD_BANK_ADDR_3)); 161 162 /* PD, SR */ 163 out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); 164 out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); 165 166 /* refresh scheme */ 167 set_wait_for_bits_clear(&mmdc->mdref, 168 CONFIG_SYS_MMDC_CORE_REFRESH_CTL, 169 START_REFRESH); 170 171 /* disable CON_REQ */ 172 out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); 173 } 174 175 int dram_init(void) 176 { 177 mmdc_init(); 178 179 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 180 181 return 0; 182 } 183 184 int board_eth_init(bd_t *bis) 185 { 186 return pci_eth_init(bis); 187 } 188 189 int board_early_init_f(void) 190 { 191 fsl_lsch2_early_init_f(); 192 193 return 0; 194 } 195 196 int board_init(void) 197 { 198 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 199 /* 200 * Set CCI-400 control override register to enable barrier 201 * transaction 202 */ 203 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 204 205 #ifdef CONFIG_ENV_IS_NOWHERE 206 gd->env_addr = (ulong)&default_environment[0]; 207 #endif 208 209 return 0; 210 } 211 212 int ft_board_setup(void *blob, bd_t *bd) 213 { 214 arch_fixup_fdt(blob); 215 216 ft_cpu_setup(blob, bd); 217 218 return 0; 219 } 220