1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <hwconfig.h> 14 #include <environment.h> 15 #include <fsl_mmdc.h> 16 #include <netdev.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) 21 { 22 int timeout = 1000; 23 24 out_be32(ptr, value); 25 26 while (in_be32(ptr) & bits) { 27 udelay(100); 28 timeout--; 29 } 30 if (timeout <= 0) 31 puts("Error: wait for clear timeout.\n"); 32 } 33 34 int checkboard(void) 35 { 36 puts("Board: LS1012AFRDM "); 37 38 return 0; 39 } 40 41 void mmdc_init(void) 42 { 43 struct mmdc_p_regs *mmdc = 44 (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; 45 46 out_be32(&mmdc->mdscr, CONFIGURATION_REQ); 47 48 /* configure timing parms */ 49 out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); 50 out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); 51 out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); 52 out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); 53 54 /* other parms */ 55 out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); 56 out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); 57 out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); 58 out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); 59 60 /* out of reset delays */ 61 out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); 62 63 /* physical parms */ 64 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); 65 out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); 66 67 /* Enable MMDC */ 68 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); 69 70 /* dram init sequence: update MRs */ 71 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | 72 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); 73 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 74 CMD_BANK_ADDR_3)); 75 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 76 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); 77 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | 78 CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | 79 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); 80 81 /* dram init sequence: ZQCL */ 82 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 83 CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); 84 set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 85 CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, 86 FORCE_ZQ_AUTO_CALIBRATION); 87 88 /* Calibrations now: wr lvl */ 89 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | 90 CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 91 CMD_BANK_ADDR_1)); 92 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); 93 set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); 94 95 mdelay(1); 96 97 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 98 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); 99 out_be32(&mmdc->mdscr, CONFIGURATION_REQ); 100 101 mdelay(1); 102 103 /* Calibrations now: Read DQS gating calibration */ 104 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 105 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); 106 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 107 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); 108 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); 109 out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); 110 set_wait_for_bits_clear(&mmdc->mpdgctrl0, 111 AUTO_RD_DQS_GATING_CALIBRATION_EN, 112 AUTO_RD_DQS_GATING_CALIBRATION_EN); 113 114 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 115 CMD_BANK_ADDR_3)); 116 117 /* Calibrations now: Read calibration */ 118 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | 119 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); 120 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | 121 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); 122 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); 123 set_wait_for_bits_clear(&mmdc->mprddlhwctl, 124 AUTO_RD_CALIBRATION_EN, 125 AUTO_RD_CALIBRATION_EN); 126 127 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | 128 CMD_BANK_ADDR_3)); 129 130 /* PD, SR */ 131 out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); 132 out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); 133 134 /* refresh scheme */ 135 set_wait_for_bits_clear(&mmdc->mdref, 136 CONFIG_SYS_MMDC_CORE_REFRESH_CTL, 137 START_REFRESH); 138 139 /* disable CON_REQ */ 140 out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); 141 } 142 143 int dram_init(void) 144 { 145 mmdc_init(); 146 147 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 148 149 return 0; 150 } 151 152 int board_eth_init(bd_t *bis) 153 { 154 return pci_eth_init(bis); 155 } 156 157 int board_early_init_f(void) 158 { 159 fsl_lsch2_early_init_f(); 160 161 return 0; 162 } 163 164 int board_init(void) 165 { 166 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 167 /* 168 * Set CCI-400 control override register to enable barrier 169 * transaction 170 */ 171 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 172 173 #ifdef CONFIG_ENV_IS_NOWHERE 174 gd->env_addr = (ulong)&default_environment[0]; 175 #endif 176 177 return 0; 178 } 179 180 int ft_board_setup(void *blob, bd_t *bd) 181 { 182 arch_fixup_fdt(blob); 183 184 ft_cpu_setup(blob, bd); 185 186 return 0; 187 } 188