1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <hwconfig.h> 14 #include <environment.h> 15 #include <fsl_mmdc.h> 16 #include <netdev.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 int checkboard(void) 21 { 22 puts("Board: LS1012AFRDM "); 23 24 return 0; 25 } 26 27 int dram_init(void) 28 { 29 static const struct fsl_mmdc_info mparam = { 30 0x04180000, /* mdctl */ 31 0x00030035, /* mdpdc */ 32 0x12554000, /* mdotc */ 33 0xbabf7954, /* mdcfg0 */ 34 0xdb328f64, /* mdcfg1 */ 35 0x01ff00db, /* mdcfg2 */ 36 0x00001680, /* mdmisc */ 37 0x0f3c8000, /* mdref */ 38 0x00002000, /* mdrwd */ 39 0x00bf1023, /* mdor */ 40 0x0000003f, /* mdasp */ 41 0x0000022a, /* mpodtctrl */ 42 0xa1390003, /* mpzqhwctrl */ 43 }; 44 45 mmdc_init(&mparam); 46 47 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 48 49 return 0; 50 } 51 52 int board_eth_init(bd_t *bis) 53 { 54 return pci_eth_init(bis); 55 } 56 57 int board_early_init_f(void) 58 { 59 fsl_lsch2_early_init_f(); 60 61 return 0; 62 } 63 64 int board_init(void) 65 { 66 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 67 /* 68 * Set CCI-400 control override register to enable barrier 69 * transaction 70 */ 71 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 72 73 #ifdef CONFIG_ENV_IS_NOWHERE 74 gd->env_addr = (ulong)&default_environment[0]; 75 #endif 76 77 return 0; 78 } 79 80 int ft_board_setup(void *blob, bd_t *bd) 81 { 82 arch_fixup_fdt(blob); 83 84 ft_cpu_setup(blob, bd); 85 86 return 0; 87 } 88 89 void dram_init_banksize(void) 90 { 91 /* 92 * gd->arch.secure_ram tracks the location of secure memory. 93 * It was set as if the memory starts from 0. 94 * The address needs to add the offset of its bank. 95 */ 96 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 97 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { 98 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; 99 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; 100 gd->bd->bi_dram[1].size = gd->ram_size - 101 CONFIG_SYS_DDR_BLOCK1_SIZE; 102 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 103 gd->arch.secure_ram = gd->bd->bi_dram[1].start + 104 gd->arch.secure_ram - 105 CONFIG_SYS_DDR_BLOCK1_SIZE; 106 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 107 #endif 108 } else { 109 gd->bd->bi_dram[0].size = gd->ram_size; 110 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 111 gd->arch.secure_ram = gd->bd->bi_dram[0].start + 112 gd->arch.secure_ram; 113 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 114 #endif 115 } 116 } 117