1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <asm/mmu.h> 27 #include <asm/processor.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_law.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 #include <malloc.h> 36 #include <fm_eth.h> 37 #include <fsl_mdio.h> 38 #include <miiphy.h> 39 #include <phy.h> 40 41 #include "../common/ngpixis.h" 42 #include "../common/fman.h" 43 #include <asm/fsl_dtsec.h> 44 45 #define EMI_NONE 0xffffffff 46 #define EMI_MASK 0xf0000000 47 #define EMI1_RGMII 0x0 48 #define EMI1_SLOT3 0x80000000 /* bank1 EFGH */ 49 #define EMI1_SLOT4 0x40000000 /* bank2 ABCD */ 50 #define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */ 51 #define EMI2_SLOT4 0x10000000 /* bank2 ABCD */ 52 #define EMI2_SLOT5 0x30000000 /* bank3 ABCD */ 53 #define EMI1_MASK 0xc0000000 54 #define EMI2_MASK 0x30000000 55 56 static int mdio_mux[NUM_FM_PORTS]; 57 58 static char *mdio_names[16] = { 59 "P4080DS_MDIO0", 60 "P4080DS_MDIO1", 61 NULL, 62 "P4080DS_MDIO3", 63 "P4080DS_MDIO4", 64 NULL, NULL, NULL, 65 "P4080DS_MDIO8", 66 NULL, NULL, NULL, 67 "P4080DS_MDIO12", 68 NULL, NULL, NULL, 69 }; 70 71 static char *p4080ds_mdio_name_for_muxval(u32 muxval) 72 { 73 return mdio_names[(muxval & EMI_MASK) >> 28]; 74 } 75 76 struct mii_dev *mii_dev_for_muxval(u32 muxval) 77 { 78 struct mii_dev *bus; 79 char *name = p4080ds_mdio_name_for_muxval(muxval); 80 81 if (!name) { 82 printf("No bus for muxval %x\n", muxval); 83 return NULL; 84 } 85 86 bus = miiphy_get_dev_by_name(name); 87 88 if (!bus) { 89 printf("No bus by name %s\n", name); 90 return NULL; 91 } 92 93 return bus; 94 } 95 96 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 97 int board_phy_config(struct phy_device *phydev) 98 { 99 /* 100 * If this is the 10G PHY, and we switched it to fiber, 101 * we need to reset the serdes link for SERDES9 102 */ 103 if ((phydev->port == PORT_FIBRE) && (phydev->drv->uid == 0x00a19410)) { 104 enum srds_prtcl device; 105 106 switch (phydev->addr) { 107 case 4: 108 device = XAUI_FM1; 109 break; 110 case 0: 111 device = XAUI_FM2; 112 break; 113 default: 114 device = NONE; 115 } 116 117 serdes_reset_rx(device); 118 } 119 120 return 0; 121 } 122 #endif 123 124 struct p4080ds_mdio { 125 u32 muxval; 126 struct mii_dev *realbus; 127 }; 128 129 static void p4080ds_mux_mdio(u32 muxval) 130 { 131 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 132 uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK); 133 gpioval |= muxval; 134 135 out_be32(&pgpio->gpdat, gpioval); 136 } 137 138 static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad, 139 int regnum) 140 { 141 struct p4080ds_mdio *priv = bus->priv; 142 143 p4080ds_mux_mdio(priv->muxval); 144 145 return priv->realbus->read(priv->realbus, addr, devad, regnum); 146 } 147 148 static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad, 149 int regnum, u16 value) 150 { 151 struct p4080ds_mdio *priv = bus->priv; 152 153 p4080ds_mux_mdio(priv->muxval); 154 155 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 156 } 157 158 static int p4080ds_mdio_reset(struct mii_dev *bus) 159 { 160 struct p4080ds_mdio *priv = bus->priv; 161 162 return priv->realbus->reset(priv->realbus); 163 } 164 165 static int p4080ds_mdio_init(char *realbusname, u32 muxval) 166 { 167 struct p4080ds_mdio *pmdio; 168 struct mii_dev *bus = mdio_alloc(); 169 170 if (!bus) { 171 printf("Failed to allocate P4080DS MDIO bus\n"); 172 return -1; 173 } 174 175 pmdio = malloc(sizeof(*pmdio)); 176 if (!pmdio) { 177 printf("Failed to allocate P4080DS private data\n"); 178 free(bus); 179 return -1; 180 } 181 182 bus->read = p4080ds_mdio_read; 183 bus->write = p4080ds_mdio_write; 184 bus->reset = p4080ds_mdio_reset; 185 sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval)); 186 187 pmdio->realbus = miiphy_get_dev_by_name(realbusname); 188 189 if (!pmdio->realbus) { 190 printf("No bus with name %s\n", realbusname); 191 free(bus); 192 free(pmdio); 193 return -1; 194 } 195 196 pmdio->muxval = muxval; 197 bus->priv = pmdio; 198 199 return mdio_register(bus); 200 } 201 202 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, 203 enum fm_port port, int offset) 204 { 205 if (mdio_mux[port] == EMI1_RGMII) 206 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); 207 208 if (mdio_mux[port] == EMI1_SLOT3) { 209 int idx = port - FM2_DTSEC1 + 5; 210 char phy[16]; 211 212 sprintf(phy, "phy%d_slot3", idx); 213 214 fdt_set_phy_handle(blob, prop, pa, phy); 215 } 216 } 217 218 void fdt_fixup_board_enet(void *fdt) 219 { 220 int i; 221 222 /* 223 * P4080DS can be configured in many different ways, supporting a number 224 * of combinations of ethernet devices and phy types. In order to 225 * have just one device tree for all of those configurations, we fix up 226 * the tree here. By default, the device tree configures FM1 and FM2 227 * for SGMII, and configures XAUI on both 10G interfaces. So we have 228 * a number of different variables to track: 229 * 230 * 1) Whether the device is configured at all. Whichever devices are 231 * not enabled should be disabled by setting the "status" property 232 * to "disabled". 233 * 2) What the PHY interface is. If this is an RGMII connection, 234 * we should change the "phy-connection-type" property to 235 * "rgmii" 236 * 3) Which PHY is being used. Because the MDIO buses are muxed, 237 * we need to redirect the "phy-handle" property to point at the 238 * PHY on the right slot/bus. 239 */ 240 241 /* We've got six MDIO nodes that may or may not need to exist */ 242 fdt_status_disabled_by_alias(fdt, "emi1_slot3"); 243 fdt_status_disabled_by_alias(fdt, "emi1_slot4"); 244 fdt_status_disabled_by_alias(fdt, "emi1_slot5"); 245 fdt_status_disabled_by_alias(fdt, "emi2_slot4"); 246 fdt_status_disabled_by_alias(fdt, "emi2_slot5"); 247 248 for (i = 0; i < NUM_FM_PORTS; i++) { 249 switch (mdio_mux[i]) { 250 case EMI1_SLOT3: 251 fdt_status_okay_by_alias(fdt, "emi1_slot3"); 252 break; 253 case EMI1_SLOT4: 254 fdt_status_okay_by_alias(fdt, "emi1_slot4"); 255 break; 256 case EMI1_SLOT5: 257 fdt_status_okay_by_alias(fdt, "emi1_slot5"); 258 break; 259 case EMI2_SLOT4: 260 fdt_status_okay_by_alias(fdt, "emi2_slot4"); 261 break; 262 case EMI2_SLOT5: 263 fdt_status_okay_by_alias(fdt, "emi2_slot5"); 264 break; 265 } 266 } 267 } 268 269 enum board_slots { 270 SLOT1 = 1, 271 SLOT2, 272 SLOT3, 273 SLOT4, 274 SLOT5, 275 SLOT6, 276 }; 277 278 int board_eth_init(bd_t *bis) 279 { 280 #ifdef CONFIG_FMAN_ENET 281 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); 282 struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; 283 int i; 284 struct fsl_pq_mdio_info dtsec_mdio_info; 285 struct tgec_mdio_info tgec_mdio_info; 286 287 u8 lane_to_slot[] = { 288 SLOT1, /* 0 - Bank 1:A */ 289 SLOT1, /* 1 - Bank 1:B */ 290 SLOT2, /* 2 - Bank 1:C */ 291 SLOT2, /* 3 - Bank 1:D */ 292 SLOT3, /* 4 - Bank 1:E */ 293 SLOT3, /* 5 - Bank 1:F */ 294 SLOT3, /* 6 - Bank 1:G */ 295 SLOT3, /* 7 - Bank 1:H */ 296 SLOT6, /* 8 - Bank 1:I */ 297 SLOT6, /* 9 - Bank 1:J */ 298 SLOT4, /* 10 - Bank 2:A */ 299 SLOT4, /* 11 - Bank 2:B */ 300 SLOT4, /* 12 - Bank 2:C */ 301 SLOT4, /* 13 - Bank 2:D */ 302 SLOT5, /* 14 - Bank 3:A */ 303 SLOT5, /* 15 - Bank 3:B */ 304 SLOT5, /* 16 - Bank 3:C */ 305 SLOT5, /* 17 - Bank 3:D */ 306 }; 307 308 /* 309 * Set TBIPA on FM1@DTSEC1. This is needed for configurations 310 * where FM1@DTSEC1 isn't used directly, since it provides 311 * MDIO for other ports. 312 */ 313 out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); 314 315 /* Initialize the mdio_mux array so we can recognize empty elements */ 316 for (i = 0; i < NUM_FM_PORTS; i++) 317 mdio_mux[i] = EMI_NONE; 318 319 /* The first 4 GPIOs are outputs to control MDIO bus muxing */ 320 out_be32(&pgpio->gpdir, EMI_MASK); 321 322 dtsec_mdio_info.regs = 323 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; 324 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 325 326 /* Register the 1G MDIO bus */ 327 fsl_pq_mdio_init(bis, &dtsec_mdio_info); 328 329 tgec_mdio_info.regs = 330 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 331 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 332 333 /* Register the 10G MDIO bus */ 334 fm_tgec_mdio_init(bis, &tgec_mdio_info); 335 336 /* Register the 6 muxing front-ends to the MDIO buses */ 337 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); 338 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); 339 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); 340 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); 341 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4); 342 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5); 343 344 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); 345 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); 346 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); 347 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); 348 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); 349 350 #if (CONFIG_SYS_NUM_FMAN == 2) 351 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); 352 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); 353 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR); 354 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR); 355 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); 356 #endif 357 358 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 359 int idx = i - FM1_DTSEC1, lane, slot; 360 switch (fm_info_get_enet_if(i)) { 361 case PHY_INTERFACE_MODE_SGMII: 362 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); 363 if (lane < 0) 364 break; 365 slot = lane_to_slot[lane]; 366 switch (slot) { 367 case SLOT3: 368 mdio_mux[i] = EMI1_SLOT3; 369 fm_info_set_mdio(i, 370 mii_dev_for_muxval(mdio_mux[i])); 371 break; 372 case SLOT4: 373 mdio_mux[i] = EMI1_SLOT4; 374 fm_info_set_mdio(i, 375 mii_dev_for_muxval(mdio_mux[i])); 376 break; 377 case SLOT5: 378 mdio_mux[i] = EMI1_SLOT5; 379 fm_info_set_mdio(i, 380 mii_dev_for_muxval(mdio_mux[i])); 381 break; 382 }; 383 break; 384 case PHY_INTERFACE_MODE_RGMII: 385 fm_info_set_phy_address(i, 0); 386 mdio_mux[i] = EMI1_RGMII; 387 fm_info_set_mdio(i, 388 mii_dev_for_muxval(mdio_mux[i])); 389 break; 390 default: 391 break; 392 } 393 } 394 395 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { 396 int idx = i - FM1_10GEC1, lane, slot; 397 switch (fm_info_get_enet_if(i)) { 398 case PHY_INTERFACE_MODE_XGMII: 399 lane = serdes_get_first_lane(XAUI_FM1 + idx); 400 if (lane < 0) 401 break; 402 slot = lane_to_slot[lane]; 403 switch (slot) { 404 case SLOT4: 405 mdio_mux[i] = EMI2_SLOT4; 406 fm_info_set_mdio(i, 407 mii_dev_for_muxval(mdio_mux[i])); 408 break; 409 case SLOT5: 410 mdio_mux[i] = EMI2_SLOT5; 411 fm_info_set_mdio(i, 412 mii_dev_for_muxval(mdio_mux[i])); 413 break; 414 }; 415 break; 416 default: 417 break; 418 } 419 } 420 421 #if (CONFIG_SYS_NUM_FMAN == 2) 422 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { 423 int idx = i - FM2_DTSEC1, lane, slot; 424 switch (fm_info_get_enet_if(i)) { 425 case PHY_INTERFACE_MODE_SGMII: 426 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); 427 if (lane < 0) 428 break; 429 slot = lane_to_slot[lane]; 430 switch (slot) { 431 case SLOT3: 432 mdio_mux[i] = EMI1_SLOT3; 433 fm_info_set_mdio(i, 434 mii_dev_for_muxval(mdio_mux[i])); 435 break; 436 case SLOT4: 437 mdio_mux[i] = EMI1_SLOT4; 438 fm_info_set_mdio(i, 439 mii_dev_for_muxval(mdio_mux[i])); 440 break; 441 case SLOT5: 442 mdio_mux[i] = EMI1_SLOT5; 443 fm_info_set_mdio(i, 444 mii_dev_for_muxval(mdio_mux[i])); 445 break; 446 }; 447 break; 448 case PHY_INTERFACE_MODE_RGMII: 449 fm_info_set_phy_address(i, 0); 450 mdio_mux[i] = EMI1_RGMII; 451 fm_info_set_mdio(i, 452 mii_dev_for_muxval(mdio_mux[i])); 453 break; 454 default: 455 break; 456 } 457 } 458 459 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { 460 int idx = i - FM2_10GEC1, lane, slot; 461 switch (fm_info_get_enet_if(i)) { 462 case PHY_INTERFACE_MODE_XGMII: 463 lane = serdes_get_first_lane(XAUI_FM2 + idx); 464 if (lane < 0) 465 break; 466 slot = lane_to_slot[lane]; 467 switch (slot) { 468 case SLOT4: 469 mdio_mux[i] = EMI2_SLOT4; 470 fm_info_set_mdio(i, 471 mii_dev_for_muxval(mdio_mux[i])); 472 break; 473 case SLOT5: 474 mdio_mux[i] = EMI2_SLOT5; 475 fm_info_set_mdio(i, 476 mii_dev_for_muxval(mdio_mux[i])); 477 break; 478 }; 479 break; 480 default: 481 break; 482 } 483 } 484 #endif 485 486 cpu_eth_init(bis); 487 #endif /* CONFIG_FMAN_ENET */ 488 489 return pci_eth_init(bis); 490 } 491