1 /* 2 * Copyright 2011 Freescale Semiconductor 3 * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * This file provides support for the QIXIS of some Freescale reference boards. 8 */ 9 10 #include <common.h> 11 #include <command.h> 12 #include <asm/io.h> 13 #include <linux/time.h> 14 #include <i2c.h> 15 #include "qixis.h" 16 17 #ifdef CONFIG_SYS_I2C_FPGA_ADDR 18 u8 qixis_read_i2c(unsigned int reg) 19 { 20 return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg); 21 } 22 23 void qixis_write_i2c(unsigned int reg, u8 value) 24 { 25 u8 val = value; 26 i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val); 27 } 28 #endif 29 30 #ifdef QIXIS_BASE 31 u8 qixis_read(unsigned int reg) 32 { 33 void *p = (void *)QIXIS_BASE; 34 35 return in_8(p + reg); 36 } 37 38 void qixis_write(unsigned int reg, u8 value) 39 { 40 void *p = (void *)QIXIS_BASE; 41 42 out_8(p + reg, value); 43 } 44 #endif 45 46 u16 qixis_read_minor(void) 47 { 48 u16 minor; 49 50 /* this data is in little endian */ 51 QIXIS_WRITE(tagdata, 5); 52 minor = QIXIS_READ(tagdata); 53 QIXIS_WRITE(tagdata, 6); 54 minor += QIXIS_READ(tagdata) << 8; 55 56 return minor; 57 } 58 59 char *qixis_read_time(char *result) 60 { 61 time_t time = 0; 62 int i; 63 64 /* timestamp is in 32-bit big endian */ 65 for (i = 8; i <= 11; i++) { 66 QIXIS_WRITE(tagdata, i); 67 time = (time << 8) + QIXIS_READ(tagdata); 68 } 69 70 return ctime_r(&time, result); 71 } 72 73 char *qixis_read_tag(char *buf) 74 { 75 int i; 76 char tag, *ptr = buf; 77 78 for (i = 16; i <= 63; i++) { 79 QIXIS_WRITE(tagdata, i); 80 tag = QIXIS_READ(tagdata); 81 *(ptr++) = tag; 82 if (!tag) 83 break; 84 } 85 if (i > 63) 86 *ptr = '\0'; 87 88 return buf; 89 } 90 91 /* 92 * return the string of binary of u8 in the format of 93 * 1010 10_0. The masked bit is filled as underscore. 94 */ 95 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf) 96 { 97 char *ptr; 98 int i; 99 100 ptr = buf; 101 for (i = 0x80; i > 0x08 ; i >>= 1, ptr++) 102 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); 103 *(ptr++) = ' '; 104 for (i = 0x08; i > 0 ; i >>= 1, ptr++) 105 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); 106 107 *ptr = '\0'; 108 109 return buf; 110 } 111 112 #ifdef QIXIS_RST_FORCE_MEM 113 void board_assert_mem_reset(void) 114 { 115 u8 rst; 116 117 rst = QIXIS_READ(rst_frc[0]); 118 if (!(rst & QIXIS_RST_FORCE_MEM)) 119 QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM); 120 } 121 122 void board_deassert_mem_reset(void) 123 { 124 u8 rst; 125 126 rst = QIXIS_READ(rst_frc[0]); 127 if (rst & QIXIS_RST_FORCE_MEM) 128 QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM); 129 } 130 #endif 131 132 void qixis_reset(void) 133 { 134 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); 135 } 136 137 void qixis_bank_reset(void) 138 { 139 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); 140 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); 141 } 142 143 static void __maybe_unused set_lbmap(int lbmap) 144 { 145 u8 reg; 146 147 reg = QIXIS_READ(brdcfg[0]); 148 reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap; 149 QIXIS_WRITE(brdcfg[0], reg); 150 } 151 152 static void __maybe_unused set_rcw_src(int rcw_src) 153 { 154 u8 reg; 155 156 reg = QIXIS_READ(dutcfg[1]); 157 reg = (reg & ~1) | (rcw_src & 1); 158 QIXIS_WRITE(dutcfg[1], reg); 159 QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff); 160 } 161 162 static void qixis_dump_regs(void) 163 { 164 int i; 165 166 printf("id = %02x\n", QIXIS_READ(id)); 167 printf("arch = %02x\n", QIXIS_READ(arch)); 168 printf("scver = %02x\n", QIXIS_READ(scver)); 169 printf("model = %02x\n", QIXIS_READ(model)); 170 printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl)); 171 printf("aux = %02x\n", QIXIS_READ(aux)); 172 for (i = 0; i < 16; i++) 173 printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i])); 174 for (i = 0; i < 16; i++) 175 printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i])); 176 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), 177 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); 178 printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]), 179 QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2])); 180 printf("aux = %02x\n", QIXIS_READ(aux)); 181 printf("watch = %02x\n", QIXIS_READ(watch)); 182 printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys)); 183 printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl)); 184 printf("present = %02x\n", QIXIS_READ(present)); 185 printf("present2 = %02x\n", QIXIS_READ(present2)); 186 printf("clk_spd = %02x\n", QIXIS_READ(clk_spd)); 187 printf("stat_dut = %02x\n", QIXIS_READ(stat_dut)); 188 printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); 189 printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); 190 } 191 192 static void __qixis_dump_switch(void) 193 { 194 puts("Reverse engineering switch is not implemented for this board\n"); 195 } 196 197 void qixis_dump_switch(void) 198 __attribute__((weak, alias("__qixis_dump_switch"))); 199 200 int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 201 { 202 int i; 203 204 if (argc <= 1) { 205 set_lbmap(QIXIS_LBMAP_DFLTBANK); 206 qixis_reset(); 207 } else if (strcmp(argv[1], "altbank") == 0) { 208 set_lbmap(QIXIS_LBMAP_ALTBANK); 209 qixis_bank_reset(); 210 } else if (strcmp(argv[1], "nand") == 0) { 211 #ifdef QIXIS_LBMAP_NAND 212 QIXIS_WRITE(rst_ctl, 0x30); 213 QIXIS_WRITE(rcfg_ctl, 0); 214 set_lbmap(QIXIS_LBMAP_NAND); 215 set_rcw_src(QIXIS_RCW_SRC_NAND); 216 QIXIS_WRITE(rcfg_ctl, 0x20); 217 QIXIS_WRITE(rcfg_ctl, 0x21); 218 #else 219 printf("Not implemented\n"); 220 #endif 221 } else if (strcmp(argv[1], "sd") == 0) { 222 #ifdef QIXIS_LBMAP_SD 223 QIXIS_WRITE(rst_ctl, 0x30); 224 QIXIS_WRITE(rcfg_ctl, 0); 225 set_lbmap(QIXIS_LBMAP_SD); 226 set_rcw_src(QIXIS_RCW_SRC_SD); 227 QIXIS_WRITE(rcfg_ctl, 0x20); 228 QIXIS_WRITE(rcfg_ctl, 0x21); 229 #else 230 printf("Not implemented\n"); 231 #endif 232 } else if (strcmp(argv[1], "sd_qspi") == 0) { 233 #ifdef QIXIS_LBMAP_SD_QSPI 234 QIXIS_WRITE(rst_ctl, 0x30); 235 QIXIS_WRITE(rcfg_ctl, 0); 236 set_lbmap(QIXIS_LBMAP_SD_QSPI); 237 set_rcw_src(QIXIS_RCW_SRC_SD); 238 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); 239 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); 240 #else 241 printf("Not implemented\n"); 242 #endif 243 } else if (strcmp(argv[1], "qspi") == 0) { 244 #ifdef QIXIS_LBMAP_QSPI 245 QIXIS_WRITE(rst_ctl, 0x30); 246 QIXIS_WRITE(rcfg_ctl, 0); 247 set_lbmap(QIXIS_LBMAP_QSPI); 248 set_rcw_src(QIXIS_RCW_SRC_QSPI); 249 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); 250 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); 251 #else 252 printf("Not implemented\n"); 253 #endif 254 } else if (strcmp(argv[1], "watchdog") == 0) { 255 static char *period[9] = {"2s", "4s", "8s", "16s", "32s", 256 "1min", "2min", "4min", "8min"}; 257 u8 rcfg = QIXIS_READ(rcfg_ctl); 258 259 if (argv[2] == NULL) { 260 printf("qixis watchdog <watchdog_period>\n"); 261 return 0; 262 } 263 for (i = 0; i < ARRAY_SIZE(period); i++) { 264 if (strcmp(argv[2], period[i]) == 0) { 265 /* disable watchdog */ 266 QIXIS_WRITE(rcfg_ctl, 267 rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE); 268 QIXIS_WRITE(watch, ((i<<2) - 1)); 269 QIXIS_WRITE(rcfg_ctl, rcfg); 270 return 0; 271 } 272 } 273 } else if (strcmp(argv[1], "dump") == 0) { 274 qixis_dump_regs(); 275 return 0; 276 } else if (strcmp(argv[1], "switch") == 0) { 277 qixis_dump_switch(); 278 return 0; 279 } else { 280 printf("Invalid option: %s\n", argv[1]); 281 return 1; 282 } 283 284 return 0; 285 } 286 287 U_BOOT_CMD( 288 qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd, 289 "Reset the board using the FPGA sequencer", 290 "- hard reset to default bank\n" 291 "qixis_reset altbank - reset to alternate bank\n" 292 "qixis_reset nand - reset to nand\n" 293 "qixis_reset sd - reset to sd\n" 294 "qixis_reset sd_qspi - reset to sd with qspi support\n" 295 "qixis_reset qspi - reset to qspi\n" 296 "qixis watchdog <watchdog_period> - set the watchdog period\n" 297 " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" 298 "qixis_reset dump - display the QIXIS registers\n" 299 "qixis_reset switch - display switch\n" 300 ); 301