1*415a613bSKumar Gala /* 2*415a613bSKumar Gala * Copyright 2004 Freescale Semiconductor. 3*415a613bSKumar Gala * 4*415a613bSKumar Gala * See file CREDITS for list of people who contributed to this 5*415a613bSKumar Gala * project. 6*415a613bSKumar Gala * 7*415a613bSKumar Gala * This program is free software; you can redistribute it and/or 8*415a613bSKumar Gala * modify it under the terms of the GNU General Public License as 9*415a613bSKumar Gala * published by the Free Software Foundation; either version 2 of 10*415a613bSKumar Gala * the License, or (at your option) any later version. 11*415a613bSKumar Gala * 12*415a613bSKumar Gala * This program is distributed in the hope that it will be useful, 13*415a613bSKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*415a613bSKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*415a613bSKumar Gala * GNU General Public License for more details. 16*415a613bSKumar Gala * 17*415a613bSKumar Gala * You should have received a copy of the GNU General Public License 18*415a613bSKumar Gala * along with this program; if not, write to the Free Software 19*415a613bSKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20*415a613bSKumar Gala * MA 02111-1307 USA 21*415a613bSKumar Gala */ 22*415a613bSKumar Gala 23*415a613bSKumar Gala 24*415a613bSKumar Gala #include <common.h> 25*415a613bSKumar Gala 26*415a613bSKumar Gala 27*415a613bSKumar Gala /* 28*415a613bSKumar Gala * CADMUS Board System Registers 29*415a613bSKumar Gala */ 30*415a613bSKumar Gala #ifndef CFG_CADMUS_BASE_REG 31*415a613bSKumar Gala #define CFG_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) 32*415a613bSKumar Gala #endif 33*415a613bSKumar Gala 34*415a613bSKumar Gala typedef struct cadmus_reg { 35*415a613bSKumar Gala u_char cm_ver; /* Board version */ 36*415a613bSKumar Gala u_char cm_csr; /* General control/status */ 37*415a613bSKumar Gala u_char cm_rst; /* Reset control */ 38*415a613bSKumar Gala u_char cm_hsclk; /* High speed clock */ 39*415a613bSKumar Gala u_char cm_hsxclk; /* High speed clock extended */ 40*415a613bSKumar Gala u_char cm_led; /* LED data */ 41*415a613bSKumar Gala u_char cm_pci; /* PCI control/status */ 42*415a613bSKumar Gala u_char cm_dma; /* DMA control */ 43*415a613bSKumar Gala u_char cm_reserved[248]; /* Total 256 bytes */ 44*415a613bSKumar Gala } cadmus_reg_t; 45*415a613bSKumar Gala 46*415a613bSKumar Gala 47*415a613bSKumar Gala unsigned int 48*415a613bSKumar Gala get_board_version(void) 49*415a613bSKumar Gala { 50*415a613bSKumar Gala volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; 51*415a613bSKumar Gala 52*415a613bSKumar Gala return cadmus->cm_ver; 53*415a613bSKumar Gala } 54*415a613bSKumar Gala 55*415a613bSKumar Gala 56*415a613bSKumar Gala unsigned long 57*415a613bSKumar Gala get_clock_freq(void) 58*415a613bSKumar Gala { 59*415a613bSKumar Gala volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; 60*415a613bSKumar Gala 61*415a613bSKumar Gala uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ 62*415a613bSKumar Gala 63*415a613bSKumar Gala if (pci1_speed == 0) { 64*415a613bSKumar Gala return 33000000; 65*415a613bSKumar Gala } else if (pci1_speed == 1) { 66*415a613bSKumar Gala return 66000000; 67*415a613bSKumar Gala } else { 68*415a613bSKumar Gala /* Really, unknown. Be safe? */ 69*415a613bSKumar Gala return 33000000; 70*415a613bSKumar Gala } 71*415a613bSKumar Gala } 72*415a613bSKumar Gala 73*415a613bSKumar Gala 74*415a613bSKumar Gala unsigned int 75*415a613bSKumar Gala get_pci_slot(void) 76*415a613bSKumar Gala { 77*415a613bSKumar Gala volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; 78*415a613bSKumar Gala 79*415a613bSKumar Gala /* 80*415a613bSKumar Gala * PCI slot in USER bits CSR[6:7] by convention. 81*415a613bSKumar Gala */ 82*415a613bSKumar Gala return ((cadmus->cm_csr >> 6) & 0x3) + 1; 83*415a613bSKumar Gala } 84*415a613bSKumar Gala 85*415a613bSKumar Gala 86*415a613bSKumar Gala unsigned int 87*415a613bSKumar Gala get_pci_dual(void) 88*415a613bSKumar Gala { 89*415a613bSKumar Gala volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; 90*415a613bSKumar Gala 91*415a613bSKumar Gala /* 92*415a613bSKumar Gala * PCI DUAL in CM_PCI[3] 93*415a613bSKumar Gala */ 94*415a613bSKumar Gala return cadmus->cm_pci & 0x10; 95*415a613bSKumar Gala } 96