1415a613bSKumar Gala /* 2568336ecSchenhui zhao * Copyright 2004, 2011 Freescale Semiconductor. 3415a613bSKumar Gala * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5415a613bSKumar Gala */ 6415a613bSKumar Gala 7415a613bSKumar Gala 8415a613bSKumar Gala #include <common.h> 9415a613bSKumar Gala 10415a613bSKumar Gala 11415a613bSKumar Gala /* 12415a613bSKumar Gala * CADMUS Board System Registers 13415a613bSKumar Gala */ 146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_CADMUS_BASE_REG 156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) 16415a613bSKumar Gala #endif 17415a613bSKumar Gala 18415a613bSKumar Gala typedef struct cadmus_reg { 19415a613bSKumar Gala u_char cm_ver; /* Board version */ 20415a613bSKumar Gala u_char cm_csr; /* General control/status */ 21415a613bSKumar Gala u_char cm_rst; /* Reset control */ 22415a613bSKumar Gala u_char cm_hsclk; /* High speed clock */ 23415a613bSKumar Gala u_char cm_hsxclk; /* High speed clock extended */ 24415a613bSKumar Gala u_char cm_led; /* LED data */ 25415a613bSKumar Gala u_char cm_pci; /* PCI control/status */ 26415a613bSKumar Gala u_char cm_dma; /* DMA control */ 27415a613bSKumar Gala u_char cm_reserved[248]; /* Total 256 bytes */ 28415a613bSKumar Gala } cadmus_reg_t; 29415a613bSKumar Gala 30415a613bSKumar Gala 31415a613bSKumar Gala unsigned int get_board_version(void)32415a613bSKumar Galaget_board_version(void) 33415a613bSKumar Gala { 346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; 35415a613bSKumar Gala 36415a613bSKumar Gala return cadmus->cm_ver; 37415a613bSKumar Gala } 38415a613bSKumar Gala 39415a613bSKumar Gala 40415a613bSKumar Gala unsigned long get_clock_freq(void)41415a613bSKumar Galaget_clock_freq(void) 42415a613bSKumar Gala { 436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; 44415a613bSKumar Gala 45415a613bSKumar Gala uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ 46415a613bSKumar Gala 47415a613bSKumar Gala if (pci1_speed == 0) { 48568336ecSchenhui zhao return 33333333; 49415a613bSKumar Gala } else if (pci1_speed == 1) { 50568336ecSchenhui zhao return 66666666; 51415a613bSKumar Gala } else { 52415a613bSKumar Gala /* Really, unknown. Be safe? */ 53568336ecSchenhui zhao return 33333333; 54415a613bSKumar Gala } 55415a613bSKumar Gala } 56415a613bSKumar Gala 57415a613bSKumar Gala 58415a613bSKumar Gala unsigned int get_pci_slot(void)59415a613bSKumar Galaget_pci_slot(void) 60415a613bSKumar Gala { 616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; 62415a613bSKumar Gala 63415a613bSKumar Gala /* 64415a613bSKumar Gala * PCI slot in USER bits CSR[6:7] by convention. 65415a613bSKumar Gala */ 66415a613bSKumar Gala return ((cadmus->cm_csr >> 6) & 0x3) + 1; 67415a613bSKumar Gala } 68415a613bSKumar Gala 69415a613bSKumar Gala 70415a613bSKumar Gala unsigned int get_pci_dual(void)71415a613bSKumar Galaget_pci_dual(void) 72415a613bSKumar Gala { 736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; 74415a613bSKumar Gala 75415a613bSKumar Gala /* 76415a613bSKumar Gala * PCI DUAL in CM_PCI[3] 77415a613bSKumar Gala */ 78415a613bSKumar Gala return cadmus->cm_pci & 0x10; 79415a613bSKumar Gala } 80