141d91011SPrabhakar Kushwaha /* 241d91011SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc. 341d91011SPrabhakar Kushwaha * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 541d91011SPrabhakar Kushwaha */ 641d91011SPrabhakar Kushwaha 741d91011SPrabhakar Kushwaha #include <common.h> 841d91011SPrabhakar Kushwaha #include <asm/fsl_law.h> 941d91011SPrabhakar Kushwaha #include <asm/mmu.h> 1041d91011SPrabhakar Kushwaha 1141d91011SPrabhakar Kushwaha struct law_entry law_table[] = { 1241d91011SPrabhakar Kushwaha SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC), 1383e0c2bbSPrabhakar Kushwaha #ifdef CONFIG_SYS_NAND_BASE_PHYS 1441d91011SPrabhakar Kushwaha SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), 1583e0c2bbSPrabhakar Kushwaha #endif 1683e0c2bbSPrabhakar Kushwaha #ifdef CONFIG_SYS_FPGA_BASE_PHYS 1741d91011SPrabhakar Kushwaha SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), 1883e0c2bbSPrabhakar Kushwaha #endif 19*64501c66SPriyanka Jain SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, 20*64501c66SPriyanka Jain LAW_TRGT_IF_DSP_CCSR), 21*64501c66SPriyanka Jain SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M, 22*64501c66SPriyanka Jain LAW_TRGT_IF_OCN_DSP), 23*64501c66SPriyanka Jain SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K, 24*64501c66SPriyanka Jain LAW_TRGT_IF_CLASS_DSP), 25*64501c66SPriyanka Jain SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G, 26*64501c66SPriyanka Jain LAW_TRGT_IF_CLASS_DSP) 2741d91011SPrabhakar Kushwaha }; 2841d91011SPrabhakar Kushwaha 2941d91011SPrabhakar Kushwaha int num_law_entries = ARRAY_SIZE(law_table); 30