1 /* 2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Engicam S.r.l. 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <miiphy.h> 11 #include <netdev.h> 12 13 #include <asm/io.h> 14 #include <asm/gpio.h> 15 #include <linux/sizes.h> 16 17 #include <asm/arch/clock.h> 18 #include <asm/arch/crm_regs.h> 19 #include <asm/arch/iomux.h> 20 #include <asm/arch/mx6-pins.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/imx-common/iomux-v3.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 27 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 28 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 29 30 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 32 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 33 34 static iomux_v3_cfg_t const uart4_pads[] = { 35 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 36 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 37 }; 38 39 static iomux_v3_cfg_t const enet_pads[] = { 40 IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)), 41 IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL | PAD_CTL_SRE_FAST)), 42 IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)), 43 IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 44 IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 45 IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 46 IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 47 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 48 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 49 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), 50 }; 51 52 #ifdef CONFIG_FEC_MXC 53 #define ENET_PHY_RST IMX_GPIO_NR(7, 12) 54 static int setup_fec(void) 55 { 56 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 57 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 58 s32 timeout = 100000; 59 u32 reg = 0; 60 int ret; 61 62 /* Enable fec clock */ 63 setbits_le32(&ccm->CCGR1, MXC_CCM_CCGR1_ENET_MASK); 64 65 /* use 50MHz */ 66 ret = enable_fec_anatop_clock(0, ENET_50MHZ); 67 if (ret) 68 return ret; 69 70 /* Enable PLLs */ 71 reg = readl(&anatop->pll_enet); 72 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; 73 writel(reg, &anatop->pll_enet); 74 reg = readl(&anatop->pll_enet); 75 reg |= BM_ANADIG_PLL_SYS_ENABLE; 76 while (timeout--) { 77 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_SYS_LOCK) 78 break; 79 } 80 if (timeout <= 0) 81 return -EIO; 82 reg &= ~BM_ANADIG_PLL_SYS_BYPASS; 83 writel(reg, &anatop->pll_enet); 84 85 /* reset the phy */ 86 gpio_direction_output(ENET_PHY_RST, 0); 87 udelay(10000); 88 gpio_set_value(ENET_PHY_RST, 1); 89 90 return 0; 91 } 92 93 int board_eth_init(bd_t *bis) 94 { 95 int ret; 96 97 SETUP_IOMUX_PADS(enet_pads); 98 setup_fec(); 99 100 return ret = cpu_eth_init(bis); 101 } 102 #endif 103 104 #ifdef CONFIG_NAND_MXS 105 106 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) 107 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ 108 PAD_CTL_SRE_FAST) 109 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) 110 111 iomux_v3_cfg_t gpmi_pads[] = { 112 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 113 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 114 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 115 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), 116 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 117 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 118 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 119 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 120 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 121 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 122 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 123 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 124 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 125 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 126 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 127 }; 128 129 static void setup_gpmi_nand(void) 130 { 131 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 132 133 /* config gpmi nand iomux */ 134 SETUP_IOMUX_PADS(gpmi_pads); 135 136 /* gate ENFC_CLK_ROOT clock first,before clk source switch */ 137 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 138 139 /* config gpmi and bch clock to 100 MHz */ 140 clrsetbits_le32(&mxc_ccm->cs2cdr, 141 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 142 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 143 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 144 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 145 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 146 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 147 148 /* enable ENFC_CLK_ROOT clock */ 149 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 150 151 /* enable gpmi and bch clock gating */ 152 setbits_le32(&mxc_ccm->CCGR4, 153 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 154 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 155 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 156 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 157 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 158 159 /* enable apbh clock gating */ 160 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 161 } 162 #endif 163 164 int board_early_init_f(void) 165 { 166 SETUP_IOMUX_PADS(uart4_pads); 167 168 return 0; 169 } 170 171 int board_init(void) 172 { 173 /* Address of boot parameters */ 174 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 175 176 #ifdef CONFIG_NAND_MXS 177 setup_gpmi_nand(); 178 #endif 179 return 0; 180 } 181 182 int dram_init(void) 183 { 184 gd->ram_size = imx_ddr_size(); 185 186 return 0; 187 } 188 189 #ifdef CONFIG_SPL_BUILD 190 #include <libfdt.h> 191 #include <spl.h> 192 193 #include <asm/arch/crm_regs.h> 194 #include <asm/arch/mx6-ddr.h> 195 196 /* MMC board initialization is needed till adding DM support in SPL */ 197 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) 198 #include <mmc.h> 199 #include <fsl_esdhc.h> 200 201 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 202 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 203 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 204 205 static iomux_v3_cfg_t const usdhc1_pads[] = { 206 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 207 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 208 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 209 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 210 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 211 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 212 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ 213 }; 214 215 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) 216 217 struct fsl_esdhc_cfg usdhc_cfg[1] = { 218 {USDHC1_BASE_ADDR, 0, 4}, 219 }; 220 221 int board_mmc_getcd(struct mmc *mmc) 222 { 223 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 224 int ret = 0; 225 226 switch (cfg->esdhc_base) { 227 case USDHC1_BASE_ADDR: 228 ret = !gpio_get_value(USDHC1_CD_GPIO); 229 break; 230 } 231 232 return ret; 233 } 234 235 int board_mmc_init(bd_t *bis) 236 { 237 int i, ret; 238 239 /* 240 * According to the board_mmc_init() the following map is done: 241 * (U-boot device node) (Physical Port) 242 * mmc0 USDHC1 243 */ 244 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 245 switch (i) { 246 case 0: 247 SETUP_IOMUX_PADS(usdhc1_pads); 248 gpio_direction_input(USDHC1_CD_GPIO); 249 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 250 break; 251 default: 252 printf("Warning - USDHC%d controller not supporting\n", 253 i + 1); 254 return 0; 255 } 256 257 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 258 if (ret) { 259 printf("Warning: failed to initialize mmc dev %d\n", i); 260 return ret; 261 } 262 } 263 264 return 0; 265 } 266 #endif 267 268 /* 269 * Driving strength: 270 * 0x30 == 40 Ohm 271 * 0x28 == 48 Ohm 272 */ 273 274 #define IMX6DQ_DRIVE_STRENGTH 0x30 275 #define IMX6SDL_DRIVE_STRENGTH 0x28 276 277 /* configure MX6Q/DUAL mmdc DDR io registers */ 278 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 279 .dram_sdqs0 = 0x28, 280 .dram_sdqs1 = 0x28, 281 .dram_sdqs2 = 0x28, 282 .dram_sdqs3 = 0x28, 283 .dram_sdqs4 = 0x28, 284 .dram_sdqs5 = 0x28, 285 .dram_sdqs6 = 0x28, 286 .dram_sdqs7 = 0x28, 287 .dram_dqm0 = 0x28, 288 .dram_dqm1 = 0x28, 289 .dram_dqm2 = 0x28, 290 .dram_dqm3 = 0x28, 291 .dram_dqm4 = 0x28, 292 .dram_dqm5 = 0x28, 293 .dram_dqm6 = 0x28, 294 .dram_dqm7 = 0x28, 295 .dram_cas = 0x30, 296 .dram_ras = 0x30, 297 .dram_sdclk_0 = 0x30, 298 .dram_sdclk_1 = 0x30, 299 .dram_reset = 0x30, 300 .dram_sdcke0 = 0x3000, 301 .dram_sdcke1 = 0x3000, 302 .dram_sdba2 = 0x00000000, 303 .dram_sdodt0 = 0x30, 304 .dram_sdodt1 = 0x30, 305 }; 306 307 /* configure MX6Q/DUAL mmdc GRP io registers */ 308 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 309 .grp_b0ds = 0x30, 310 .grp_b1ds = 0x30, 311 .grp_b2ds = 0x30, 312 .grp_b3ds = 0x30, 313 .grp_b4ds = 0x30, 314 .grp_b5ds = 0x30, 315 .grp_b6ds = 0x30, 316 .grp_b7ds = 0x30, 317 .grp_addds = 0x30, 318 .grp_ddrmode_ctl = 0x00020000, 319 .grp_ddrpke = 0x00000000, 320 .grp_ddrmode = 0x00020000, 321 .grp_ctlds = 0x30, 322 .grp_ddr_type = 0x000c0000, 323 }; 324 325 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 326 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 327 .dram_sdclk_0 = 0x30, 328 .dram_sdclk_1 = 0x30, 329 .dram_cas = 0x30, 330 .dram_ras = 0x30, 331 .dram_reset = 0x30, 332 .dram_sdcke0 = 0x30, 333 .dram_sdcke1 = 0x30, 334 .dram_sdba2 = 0x00000000, 335 .dram_sdodt0 = 0x30, 336 .dram_sdodt1 = 0x30, 337 .dram_sdqs0 = 0x28, 338 .dram_sdqs1 = 0x28, 339 .dram_sdqs2 = 0x28, 340 .dram_sdqs3 = 0x28, 341 .dram_sdqs4 = 0x28, 342 .dram_sdqs5 = 0x28, 343 .dram_sdqs6 = 0x28, 344 .dram_sdqs7 = 0x28, 345 .dram_dqm0 = 0x28, 346 .dram_dqm1 = 0x28, 347 .dram_dqm2 = 0x28, 348 .dram_dqm3 = 0x28, 349 .dram_dqm4 = 0x28, 350 .dram_dqm5 = 0x28, 351 .dram_dqm6 = 0x28, 352 .dram_dqm7 = 0x28, 353 }; 354 355 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 356 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 357 .grp_ddr_type = 0x000c0000, 358 .grp_ddrmode_ctl = 0x00020000, 359 .grp_ddrpke = 0x00000000, 360 .grp_addds = 0x30, 361 .grp_ctlds = 0x30, 362 .grp_ddrmode = 0x00020000, 363 .grp_b0ds = 0x28, 364 .grp_b1ds = 0x28, 365 .grp_b2ds = 0x28, 366 .grp_b3ds = 0x28, 367 .grp_b4ds = 0x28, 368 .grp_b5ds = 0x28, 369 .grp_b6ds = 0x28, 370 .grp_b7ds = 0x28, 371 }; 372 373 /* mt41j256 */ 374 static struct mx6_ddr3_cfg mt41j256 = { 375 .mem_speed = 1066, 376 .density = 2, 377 .width = 16, 378 .banks = 8, 379 .rowaddr = 13, 380 .coladdr = 10, 381 .pagesz = 2, 382 .trcd = 1375, 383 .trcmin = 4875, 384 .trasmin = 3500, 385 .SRT = 0, 386 }; 387 388 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { 389 .p0_mpwldectrl0 = 0x000E0009, 390 .p0_mpwldectrl1 = 0x0018000E, 391 .p1_mpwldectrl0 = 0x00000007, 392 .p1_mpwldectrl1 = 0x00000000, 393 .p0_mpdgctrl0 = 0x43280334, 394 .p0_mpdgctrl1 = 0x031C0314, 395 .p1_mpdgctrl0 = 0x4318031C, 396 .p1_mpdgctrl1 = 0x030C0258, 397 .p0_mprddlctl = 0x3E343A40, 398 .p1_mprddlctl = 0x383C3844, 399 .p0_mpwrdlctl = 0x40404440, 400 .p1_mpwrdlctl = 0x4C3E4446, 401 }; 402 403 /* DDR 64bit */ 404 static struct mx6_ddr_sysinfo mem_q = { 405 .ddr_type = DDR_TYPE_DDR3, 406 .dsize = 2, 407 .cs1_mirror = 0, 408 /* config for full 4GB range so that get_mem_size() works */ 409 .cs_density = 32, 410 .ncs = 1, 411 .bi_on = 1, 412 .rtt_nom = 2, 413 .rtt_wr = 2, 414 .ralat = 5, 415 .walat = 0, 416 .mif3_mode = 3, 417 .rst_to_cke = 0x23, 418 .sde_to_rst = 0x10, 419 }; 420 421 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { 422 .p0_mpwldectrl0 = 0x001F0024, 423 .p0_mpwldectrl1 = 0x00110018, 424 .p1_mpwldectrl0 = 0x001F0024, 425 .p1_mpwldectrl1 = 0x00110018, 426 .p0_mpdgctrl0 = 0x4230022C, 427 .p0_mpdgctrl1 = 0x02180220, 428 .p1_mpdgctrl0 = 0x42440248, 429 .p1_mpdgctrl1 = 0x02300238, 430 .p0_mprddlctl = 0x44444A48, 431 .p1_mprddlctl = 0x46484A42, 432 .p0_mpwrdlctl = 0x38383234, 433 .p1_mpwrdlctl = 0x3C34362E, 434 }; 435 436 /* DDR 64bit 1GB */ 437 static struct mx6_ddr_sysinfo mem_dl = { 438 .dsize = 2, 439 .cs1_mirror = 0, 440 /* config for full 4GB range so that get_mem_size() works */ 441 .cs_density = 32, 442 .ncs = 1, 443 .bi_on = 1, 444 .rtt_nom = 1, 445 .rtt_wr = 1, 446 .ralat = 5, 447 .walat = 0, 448 .mif3_mode = 3, 449 .rst_to_cke = 0x23, 450 .sde_to_rst = 0x10, 451 }; 452 453 /* DDR 32bit 512MB */ 454 static struct mx6_ddr_sysinfo mem_s = { 455 .dsize = 1, 456 .cs1_mirror = 0, 457 /* config for full 4GB range so that get_mem_size() works */ 458 .cs_density = 32, 459 .ncs = 1, 460 .bi_on = 1, 461 .rtt_nom = 1, 462 .rtt_wr = 1, 463 .ralat = 5, 464 .walat = 0, 465 .mif3_mode = 3, 466 .rst_to_cke = 0x23, 467 .sde_to_rst = 0x10, 468 }; 469 470 static void ccgr_init(void) 471 { 472 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 473 474 writel(0x00003F3F, &ccm->CCGR0); 475 writel(0x0030FC00, &ccm->CCGR1); 476 writel(0x000FC000, &ccm->CCGR2); 477 writel(0x3F300000, &ccm->CCGR3); 478 writel(0xFF00F300, &ccm->CCGR4); 479 writel(0x0F0000C3, &ccm->CCGR5); 480 writel(0x000003CC, &ccm->CCGR6); 481 } 482 483 static void gpr_init(void) 484 { 485 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 486 487 /* enable AXI cache for VDOA/VPU/IPU */ 488 writel(0xF00000CF, &iomux->gpr[4]); 489 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 490 writel(0x007F007F, &iomux->gpr[6]); 491 writel(0x007F007F, &iomux->gpr[7]); 492 } 493 494 static void spl_dram_init(void) 495 { 496 if (is_mx6solo()) { 497 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 498 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); 499 } else if (is_mx6dl()) { 500 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 501 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); 502 } else if (is_mx6dq()) { 503 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); 504 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); 505 } 506 507 udelay(100); 508 } 509 510 void board_init_f(ulong dummy) 511 { 512 ccgr_init(); 513 514 /* setup AIPS and disable watchdog */ 515 arch_cpu_init(); 516 517 gpr_init(); 518 519 /* iomux */ 520 board_early_init_f(); 521 522 /* setup GP timer */ 523 timer_init(); 524 525 /* UART clocks enabled and gd valid - init serial console */ 526 preloader_console_init(); 527 528 /* DDR initialization */ 529 spl_dram_init(); 530 531 /* Clear the BSS. */ 532 memset(__bss_start, 0, __bss_end - __bss_start); 533 534 /* load/boot image from boot device */ 535 board_init_r(NULL, 0); 536 } 537 #endif 538