1 /* 2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Engicam S.r.l. 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <mmc.h> 11 12 #include <asm/io.h> 13 #include <asm/gpio.h> 14 #include <linux/sizes.h> 15 16 #include <asm/arch/clock.h> 17 #include <asm/arch/crm_regs.h> 18 #include <asm/arch/iomux.h> 19 #include <asm/arch/mx6-pins.h> 20 #include <asm/arch/sys_proto.h> 21 #include <asm/imx-common/iomux-v3.h> 22 #include <asm/imx-common/video.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 27 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 28 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 29 30 static iomux_v3_cfg_t const uart4_pads[] = { 31 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 32 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 33 }; 34 35 #ifdef CONFIG_NAND_MXS 36 37 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) 38 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ 39 PAD_CTL_SRE_FAST) 40 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) 41 42 iomux_v3_cfg_t gpmi_pads[] = { 43 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 44 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 45 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 46 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), 47 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 48 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 49 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 50 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 51 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 52 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 53 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 54 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 55 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 56 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 57 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 58 }; 59 60 static void setup_gpmi_nand(void) 61 { 62 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 63 64 /* config gpmi nand iomux */ 65 SETUP_IOMUX_PADS(gpmi_pads); 66 67 /* gate ENFC_CLK_ROOT clock first,before clk source switch */ 68 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 69 70 /* config gpmi and bch clock to 100 MHz */ 71 clrsetbits_le32(&mxc_ccm->cs2cdr, 72 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 73 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 74 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 75 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 76 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 77 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 78 79 /* enable ENFC_CLK_ROOT clock */ 80 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 81 82 /* enable gpmi and bch clock gating */ 83 setbits_le32(&mxc_ccm->CCGR4, 84 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 85 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 86 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 87 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 88 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 89 90 /* enable apbh clock gating */ 91 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 92 } 93 #endif 94 95 #if defined(CONFIG_VIDEO_IPUV3) 96 static iomux_v3_cfg_t const rgb_pads[] = { 97 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), 98 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), 99 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), 100 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), 101 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), 102 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), 103 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), 104 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), 105 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), 106 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), 107 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), 108 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), 109 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), 110 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), 111 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), 112 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), 113 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), 114 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), 115 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), 116 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), 117 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), 118 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), 119 }; 120 121 static void enable_rgb(struct display_info_t const *dev) 122 { 123 SETUP_IOMUX_PADS(rgb_pads); 124 } 125 126 struct display_info_t const displays[] = { 127 { 128 .bus = -1, 129 .addr = 0, 130 .pixfmt = IPU_PIX_FMT_RGB666, 131 .detect = NULL, 132 .enable = enable_rgb, 133 .mode = { 134 .name = "Amp-WD", 135 .refresh = 60, 136 .xres = 800, 137 .yres = 480, 138 .pixclock = 30000, 139 .left_margin = 30, 140 .right_margin = 30, 141 .upper_margin = 5, 142 .lower_margin = 5, 143 .hsync_len = 64, 144 .vsync_len = 20, 145 .sync = FB_SYNC_EXT, 146 .vmode = FB_VMODE_NONINTERLACED 147 } 148 }, 149 }; 150 151 size_t display_count = ARRAY_SIZE(displays); 152 153 static void setup_display(void) 154 { 155 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 156 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 157 int reg; 158 159 enable_ipu_clock(); 160 161 /* Turn on LDB0,IPU,IPU DI0 clocks */ 162 reg = __raw_readl(&mxc_ccm->CCGR3); 163 reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff); 164 writel(reg, &mxc_ccm->CCGR3); 165 166 /* set LDB0, LDB1 clk select to 011/011 */ 167 reg = readl(&mxc_ccm->cs2cdr); 168 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | 169 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 170 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | 171 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 172 writel(reg, &mxc_ccm->cs2cdr); 173 174 reg = readl(&mxc_ccm->cscmr2); 175 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 176 writel(reg, &mxc_ccm->cscmr2); 177 178 reg = readl(&mxc_ccm->chsccdr); 179 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << 180 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 181 writel(reg, &mxc_ccm->chsccdr); 182 183 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | 184 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | 185 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | 186 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | 187 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | 188 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | 189 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | 190 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | 191 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 192 writel(reg, &iomux->gpr[2]); 193 194 reg = readl(&iomux->gpr[3]); 195 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | 196 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << 197 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 198 writel(reg, &iomux->gpr[3]); 199 } 200 #endif /* CONFIG_VIDEO_IPUV3 */ 201 202 int board_early_init_f(void) 203 { 204 SETUP_IOMUX_PADS(uart4_pads); 205 206 return 0; 207 } 208 209 #ifdef CONFIG_ENV_IS_IN_MMC 210 static void mmc_late_init(void) 211 { 212 char cmd[32]; 213 char mmcblk[32]; 214 u32 dev_no = mmc_get_env_dev(); 215 216 setenv_ulong("mmcdev", dev_no); 217 218 /* Set mmcblk env */ 219 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); 220 setenv("mmcroot", mmcblk); 221 222 sprintf(cmd, "mmc dev %d", dev_no); 223 run_command(cmd, 0); 224 } 225 #endif 226 227 int board_late_init(void) 228 { 229 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> 230 IMX6_BMODE_SHIFT) { 231 case IMX6_BMODE_SD: 232 case IMX6_BMODE_ESD: 233 #ifdef CONFIG_ENV_IS_IN_MMC 234 mmc_late_init(); 235 #endif 236 setenv("modeboot", "mmcboot"); 237 break; 238 case IMX6_BMODE_NAND: 239 setenv("modeboot", "nandboot"); 240 break; 241 default: 242 setenv("modeboot", ""); 243 break; 244 } 245 246 if (is_mx6dq()) 247 setenv("fdt_file", "imx6q-icore.dtb"); 248 else if(is_mx6dl() || is_mx6solo()) 249 setenv("fdt_file", "imx6dl-icore.dtb"); 250 251 return 0; 252 } 253 254 int board_init(void) 255 { 256 /* Address of boot parameters */ 257 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 258 259 #ifdef CONFIG_NAND_MXS 260 setup_gpmi_nand(); 261 #endif 262 263 #ifdef CONFIG_VIDEO_IPUV3 264 setup_display(); 265 #endif 266 267 return 0; 268 } 269 270 int dram_init(void) 271 { 272 gd->ram_size = imx_ddr_size(); 273 274 return 0; 275 } 276 277 #ifdef CONFIG_SPL_BUILD 278 #include <libfdt.h> 279 #include <spl.h> 280 281 #include <asm/arch/crm_regs.h> 282 #include <asm/arch/mx6-ddr.h> 283 284 /* MMC board initialization is needed till adding DM support in SPL */ 285 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) 286 #include <mmc.h> 287 #include <fsl_esdhc.h> 288 289 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 290 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 291 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 292 293 static iomux_v3_cfg_t const usdhc1_pads[] = { 294 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 295 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 296 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 297 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 298 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 299 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 300 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ 301 }; 302 303 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) 304 305 struct fsl_esdhc_cfg usdhc_cfg[1] = { 306 {USDHC1_BASE_ADDR, 0, 4}, 307 }; 308 309 int board_mmc_getcd(struct mmc *mmc) 310 { 311 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 312 int ret = 0; 313 314 switch (cfg->esdhc_base) { 315 case USDHC1_BASE_ADDR: 316 ret = !gpio_get_value(USDHC1_CD_GPIO); 317 break; 318 } 319 320 return ret; 321 } 322 323 int board_mmc_init(bd_t *bis) 324 { 325 int i, ret; 326 327 /* 328 * According to the board_mmc_init() the following map is done: 329 * (U-boot device node) (Physical Port) 330 * mmc0 USDHC1 331 */ 332 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 333 switch (i) { 334 case 0: 335 SETUP_IOMUX_PADS(usdhc1_pads); 336 gpio_direction_input(USDHC1_CD_GPIO); 337 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 338 break; 339 default: 340 printf("Warning - USDHC%d controller not supporting\n", 341 i + 1); 342 return 0; 343 } 344 345 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 346 if (ret) { 347 printf("Warning: failed to initialize mmc dev %d\n", i); 348 return ret; 349 } 350 } 351 352 return 0; 353 } 354 #endif 355 356 /* 357 * Driving strength: 358 * 0x30 == 40 Ohm 359 * 0x28 == 48 Ohm 360 */ 361 362 #define IMX6DQ_DRIVE_STRENGTH 0x30 363 #define IMX6SDL_DRIVE_STRENGTH 0x28 364 365 /* configure MX6Q/DUAL mmdc DDR io registers */ 366 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 367 .dram_sdqs0 = 0x28, 368 .dram_sdqs1 = 0x28, 369 .dram_sdqs2 = 0x28, 370 .dram_sdqs3 = 0x28, 371 .dram_sdqs4 = 0x28, 372 .dram_sdqs5 = 0x28, 373 .dram_sdqs6 = 0x28, 374 .dram_sdqs7 = 0x28, 375 .dram_dqm0 = 0x28, 376 .dram_dqm1 = 0x28, 377 .dram_dqm2 = 0x28, 378 .dram_dqm3 = 0x28, 379 .dram_dqm4 = 0x28, 380 .dram_dqm5 = 0x28, 381 .dram_dqm6 = 0x28, 382 .dram_dqm7 = 0x28, 383 .dram_cas = 0x30, 384 .dram_ras = 0x30, 385 .dram_sdclk_0 = 0x30, 386 .dram_sdclk_1 = 0x30, 387 .dram_reset = 0x30, 388 .dram_sdcke0 = 0x3000, 389 .dram_sdcke1 = 0x3000, 390 .dram_sdba2 = 0x00000000, 391 .dram_sdodt0 = 0x30, 392 .dram_sdodt1 = 0x30, 393 }; 394 395 /* configure MX6Q/DUAL mmdc GRP io registers */ 396 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 397 .grp_b0ds = 0x30, 398 .grp_b1ds = 0x30, 399 .grp_b2ds = 0x30, 400 .grp_b3ds = 0x30, 401 .grp_b4ds = 0x30, 402 .grp_b5ds = 0x30, 403 .grp_b6ds = 0x30, 404 .grp_b7ds = 0x30, 405 .grp_addds = 0x30, 406 .grp_ddrmode_ctl = 0x00020000, 407 .grp_ddrpke = 0x00000000, 408 .grp_ddrmode = 0x00020000, 409 .grp_ctlds = 0x30, 410 .grp_ddr_type = 0x000c0000, 411 }; 412 413 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 414 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 415 .dram_sdclk_0 = 0x30, 416 .dram_sdclk_1 = 0x30, 417 .dram_cas = 0x30, 418 .dram_ras = 0x30, 419 .dram_reset = 0x30, 420 .dram_sdcke0 = 0x30, 421 .dram_sdcke1 = 0x30, 422 .dram_sdba2 = 0x00000000, 423 .dram_sdodt0 = 0x30, 424 .dram_sdodt1 = 0x30, 425 .dram_sdqs0 = 0x28, 426 .dram_sdqs1 = 0x28, 427 .dram_sdqs2 = 0x28, 428 .dram_sdqs3 = 0x28, 429 .dram_sdqs4 = 0x28, 430 .dram_sdqs5 = 0x28, 431 .dram_sdqs6 = 0x28, 432 .dram_sdqs7 = 0x28, 433 .dram_dqm0 = 0x28, 434 .dram_dqm1 = 0x28, 435 .dram_dqm2 = 0x28, 436 .dram_dqm3 = 0x28, 437 .dram_dqm4 = 0x28, 438 .dram_dqm5 = 0x28, 439 .dram_dqm6 = 0x28, 440 .dram_dqm7 = 0x28, 441 }; 442 443 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 444 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 445 .grp_ddr_type = 0x000c0000, 446 .grp_ddrmode_ctl = 0x00020000, 447 .grp_ddrpke = 0x00000000, 448 .grp_addds = 0x30, 449 .grp_ctlds = 0x30, 450 .grp_ddrmode = 0x00020000, 451 .grp_b0ds = 0x28, 452 .grp_b1ds = 0x28, 453 .grp_b2ds = 0x28, 454 .grp_b3ds = 0x28, 455 .grp_b4ds = 0x28, 456 .grp_b5ds = 0x28, 457 .grp_b6ds = 0x28, 458 .grp_b7ds = 0x28, 459 }; 460 461 /* mt41j256 */ 462 static struct mx6_ddr3_cfg mt41j256 = { 463 .mem_speed = 1066, 464 .density = 2, 465 .width = 16, 466 .banks = 8, 467 .rowaddr = 13, 468 .coladdr = 10, 469 .pagesz = 2, 470 .trcd = 1375, 471 .trcmin = 4875, 472 .trasmin = 3500, 473 .SRT = 0, 474 }; 475 476 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { 477 .p0_mpwldectrl0 = 0x000E0009, 478 .p0_mpwldectrl1 = 0x0018000E, 479 .p1_mpwldectrl0 = 0x00000007, 480 .p1_mpwldectrl1 = 0x00000000, 481 .p0_mpdgctrl0 = 0x43280334, 482 .p0_mpdgctrl1 = 0x031C0314, 483 .p1_mpdgctrl0 = 0x4318031C, 484 .p1_mpdgctrl1 = 0x030C0258, 485 .p0_mprddlctl = 0x3E343A40, 486 .p1_mprddlctl = 0x383C3844, 487 .p0_mpwrdlctl = 0x40404440, 488 .p1_mpwrdlctl = 0x4C3E4446, 489 }; 490 491 /* DDR 64bit */ 492 static struct mx6_ddr_sysinfo mem_q = { 493 .ddr_type = DDR_TYPE_DDR3, 494 .dsize = 2, 495 .cs1_mirror = 0, 496 /* config for full 4GB range so that get_mem_size() works */ 497 .cs_density = 32, 498 .ncs = 1, 499 .bi_on = 1, 500 .rtt_nom = 2, 501 .rtt_wr = 2, 502 .ralat = 5, 503 .walat = 0, 504 .mif3_mode = 3, 505 .rst_to_cke = 0x23, 506 .sde_to_rst = 0x10, 507 }; 508 509 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { 510 .p0_mpwldectrl0 = 0x001F0024, 511 .p0_mpwldectrl1 = 0x00110018, 512 .p1_mpwldectrl0 = 0x001F0024, 513 .p1_mpwldectrl1 = 0x00110018, 514 .p0_mpdgctrl0 = 0x4230022C, 515 .p0_mpdgctrl1 = 0x02180220, 516 .p1_mpdgctrl0 = 0x42440248, 517 .p1_mpdgctrl1 = 0x02300238, 518 .p0_mprddlctl = 0x44444A48, 519 .p1_mprddlctl = 0x46484A42, 520 .p0_mpwrdlctl = 0x38383234, 521 .p1_mpwrdlctl = 0x3C34362E, 522 }; 523 524 /* DDR 64bit 1GB */ 525 static struct mx6_ddr_sysinfo mem_dl = { 526 .dsize = 2, 527 .cs1_mirror = 0, 528 /* config for full 4GB range so that get_mem_size() works */ 529 .cs_density = 32, 530 .ncs = 1, 531 .bi_on = 1, 532 .rtt_nom = 1, 533 .rtt_wr = 1, 534 .ralat = 5, 535 .walat = 0, 536 .mif3_mode = 3, 537 .rst_to_cke = 0x23, 538 .sde_to_rst = 0x10, 539 }; 540 541 /* DDR 32bit 512MB */ 542 static struct mx6_ddr_sysinfo mem_s = { 543 .dsize = 1, 544 .cs1_mirror = 0, 545 /* config for full 4GB range so that get_mem_size() works */ 546 .cs_density = 32, 547 .ncs = 1, 548 .bi_on = 1, 549 .rtt_nom = 1, 550 .rtt_wr = 1, 551 .ralat = 5, 552 .walat = 0, 553 .mif3_mode = 3, 554 .rst_to_cke = 0x23, 555 .sde_to_rst = 0x10, 556 }; 557 558 static void ccgr_init(void) 559 { 560 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 561 562 writel(0x00003F3F, &ccm->CCGR0); 563 writel(0x0030FC00, &ccm->CCGR1); 564 writel(0x000FC000, &ccm->CCGR2); 565 writel(0x3F300000, &ccm->CCGR3); 566 writel(0xFF00F300, &ccm->CCGR4); 567 writel(0x0F0000C3, &ccm->CCGR5); 568 writel(0x000003CC, &ccm->CCGR6); 569 } 570 571 static void gpr_init(void) 572 { 573 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 574 575 /* enable AXI cache for VDOA/VPU/IPU */ 576 writel(0xF00000CF, &iomux->gpr[4]); 577 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 578 writel(0x007F007F, &iomux->gpr[6]); 579 writel(0x007F007F, &iomux->gpr[7]); 580 } 581 582 static void spl_dram_init(void) 583 { 584 if (is_mx6solo()) { 585 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 586 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); 587 } else if (is_mx6dl()) { 588 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 589 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); 590 } else if (is_mx6dq()) { 591 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); 592 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); 593 } 594 595 udelay(100); 596 } 597 598 void board_init_f(ulong dummy) 599 { 600 ccgr_init(); 601 602 /* setup AIPS and disable watchdog */ 603 arch_cpu_init(); 604 605 gpr_init(); 606 607 /* iomux */ 608 board_early_init_f(); 609 610 /* setup GP timer */ 611 timer_init(); 612 613 /* UART clocks enabled and gd valid - init serial console */ 614 preloader_console_init(); 615 616 /* DDR initialization */ 617 spl_dram_init(); 618 619 /* Clear the BSS. */ 620 memset(__bss_start, 0, __bss_end - __bss_start); 621 622 /* load/boot image from boot device */ 623 board_init_r(NULL, 0); 624 } 625 #endif 626