1/* Memory sub-system initialization code */ 2 3#include <config.h> 4#include <version.h> 5#include <asm/regdef.h> 6#include <asm/au1x00.h> 7#include <asm/mipsregs.h> 8 9#define AU1500_SYS_ADDR 0xB1900000 10#define sys_endian 0x0038 11#define CP0_Config0 $16 12#define CPU_SCALE ((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */ 13#define MEM_1MS ((CFG_MHZ) * 1000) 14 15 .text 16 .set noreorder 17 .set mips32 18 19 .globl lowlevel_init 20lowlevel_init: 21 /* 22 * Step 1) Establish CPU endian mode. 23 * Db1500-specific: 24 * Switch S1.1 Off(bit7 reads 1) is Little Endian 25 * Switch S1.1 On (bit7 reads 0) is Big Endian 26 */ 27#ifdef CONFIG_DBAU1550 28 li t0, MEM_STCFG2 29 li t1, 0x00000040 30 sw t1, 0(t0) 31 32 li t0, MEM_STTIME2 33 li t1, 0x22080a20 34 sw t1, 0(t0) 35 36 li t0, MEM_STADDR2 37 li t1, 0x10c03f00 38 sw t1, 0(t0) 39#else 40 li t0, MEM_STCFG1 41 li t1, 0x00000080 42 sw t1, 0(t0) 43 44 li t0, MEM_STTIME1 45 li t1, 0x22080a20 46 sw t1, 0(t0) 47 48 li t0, MEM_STADDR1 49 li t1, 0x10c03f00 50 sw t1, 0(t0) 51#endif 52 53 li t0, DB1XX0_BCSR_ADDR 54 lw t1,8(t0) 55 andi t1,t1,0x80 56 beq zero,t1,big_endian 57 nop 58little_endian: 59 60 /* Change Au1 core to little endian */ 61 li t0, AU1500_SYS_ADDR 62 li t1, 1 63 sw t1, sys_endian(t0) 64 mfc0 t2, CP0_CONFIG 65 mtc0 t2, CP0_CONFIG 66 nop 67 nop 68 69 /* Big Endian is default so nothing to do but fall through */ 70 71big_endian: 72 73 /* 74 * Step 2) Establish Status Register 75 * (set BEV, clear ERL, clear EXL, clear IE) 76 */ 77 li t1, 0x00400000 78 mtc0 t1, CP0_STATUS 79 80 /* 81 * Step 3) Establish CP0 Config0 82 * (set OD, set K0=3) 83 */ 84 li t1, 0x00080003 85 mtc0 t1, CP0_CONFIG 86 87 /* 88 * Step 4) Disable Watchpoint facilities 89 */ 90 li t1, 0x00000000 91 mtc0 t1, CP0_WATCHLO 92 mtc0 t1, CP0_IWATCHLO 93 /* 94 * Step 5) Disable the performance counters 95 */ 96 mtc0 zero, CP0_PERFORMANCE 97 nop 98 99 /* 100 * Step 6) Establish EJTAG Debug register 101 */ 102 mtc0 zero, CP0_DEBUG 103 nop 104 105 /* 106 * Step 7) Establish Cause 107 * (set IV bit) 108 */ 109 li t1, 0x00800000 110 mtc0 t1, CP0_CAUSE 111 112 /* Establish Wired (and Random) */ 113 mtc0 zero, CP0_WIRED 114 nop 115 116#ifdef CONFIG_DBAU1550 117 /* No workaround if running from ram */ 118 lui t0, 0xffc0 119 lui t3, 0xbfc0 120 and t1, ra, t0 121 bne t1, t3, noCacheJump 122 nop 123 124 /*** From AMD YAMON ***/ 125 /* 126 * Step 8) Initialize the caches 127 */ 128 li t0, (16*1024) 129 li t1, 32 130 li t2, 0x80000000 131 addu t3, t0, t2 132cacheloop: 133 cache 0, 0(t2) 134 cache 1, 0(t2) 135 addu t2, t1 136 bne t2, t3, cacheloop 137 nop 138 139 /* Save return address */ 140 move t3, ra 141 142 /* Run from cacheable space now */ 143 bal cachehere 144 nop 145cachehere: 146 li t1, ~0x20000000 /* convert to KSEG0 */ 147 and t0, ra, t1 148 addi t0, 5*4 /* 5 insns beyond cachehere */ 149 jr t0 150 nop 151 152 /* Restore return address */ 153 move ra, t3 154 155 /* 156 * Step 9) Initialize the TLB 157 */ 158 li t0, 0 # index value 159 li t1, 0x00000000 # entryhi value 160 li t2, 32 # 32 entries 161 162tlbloop: 163 /* Probe TLB for matching EntryHi */ 164 mtc0 t1, CP0_ENTRYHI 165 tlbp 166 nop 167 168 /* Examine Index[P], 1=no matching entry */ 169 mfc0 t3, CP0_INDEX 170 li t4, 0x80000000 171 and t3, t4, t3 172 addiu t1, t1, 1 # increment t1 (asid) 173 beq zero, t3, tlbloop 174 nop 175 176 /* Initialize the TLB entry */ 177 mtc0 t0, CP0_INDEX 178 mtc0 zero, CP0_ENTRYLO0 179 mtc0 zero, CP0_ENTRYLO1 180 mtc0 zero, CP0_PAGEMASK 181 tlbwi 182 183 /* Do it again */ 184 addiu t0, t0, 1 185 bne t0, t2, tlbloop 186 nop 187 188#endif /* CONFIG_DBAU1550 */ 189 190 /* First setup pll:s to make serial work ok */ 191 /* We have a 12 MHz crystal */ 192 li t0, SYS_CPUPLL 193 li t1, CPU_SCALE /* CPU clock */ 194 sw t1, 0(t0) 195 sync 196 nop 197 nop 198 199 /* wait 1mS for clocks to settle */ 200 li t1, MEM_1MS 2011: add t1, -1 202 bne t1, zero, 1b 203 nop 204 /* Setup AUX PLL */ 205 li t0, SYS_AUXPLL 206 li t1, 0x20 /* 96 MHz */ 207 sw t1, 0(t0) /* aux pll */ 208 sync 209 210#ifdef CONFIG_DBAU1550 211 /* Static memory controller */ 212 /* RCE0 - can not change while fetching, do so from icache */ 213 move t2, ra /* Store return address */ 214 bal getAddr 215 nop 216 217getAddr: 218 move t1, ra 219 move ra, t2 /* Move return addess back */ 220 221 cache 0x14,0(t1) 222 cache 0x14,32(t1) 223 /*** /From YAMON ***/ 224 225noCacheJump: 226#endif /* CONFIG_DBAU1550 */ 227 228#ifdef CONFIG_DBAU1550 229 li t0, MEM_STTIME0 230 li t1, 0x040181D7 231 sw t1, 0(t0) 232 233 /* RCE0 AMD MirrorBit Flash (?) */ 234 li t0, MEM_STCFG0 235 li t1, 0x00000003 236 sw t1, 0(t0) 237 238 li t0, MEM_STADDR0 239 li t1, 0x11803E00 240 sw t1, 0(t0) 241#else /* CONFIG_DBAU1550 */ 242 li t0, MEM_STTIME0 243 li t1, 0x040181D7 244 sw t1, 0(t0) 245 246 /* RCE0 AMD 29LV640M MirrorBit Flash */ 247 li t0, MEM_STCFG0 248 li t1, 0x00000013 249 sw t1, 0(t0) 250 251 li t0, MEM_STADDR0 252 li t1, 0x11E03F80 253 sw t1, 0(t0) 254#endif /* CONFIG_DBAU1550 */ 255 256 /* RCE1 CPLD Board Logic */ 257 li t0, MEM_STCFG1 258 li t1, 0x00000080 259 sw t1, 0(t0) 260 261 li t0, MEM_STTIME1 262 li t1, 0x22080a20 263 sw t1, 0(t0) 264 265 li t0, MEM_STADDR1 266 li t1, 0x10c03f00 267 sw t1, 0(t0) 268 269#ifdef CONFIG_DBAU1550 270 /* RCE2 CPLD Board Logic */ 271 li t0, MEM_STCFG2 272 li t1, 0x00000040 273 sw t1, 0(t0) 274 275 li t0, MEM_STTIME2 276 li t1, 0x22080a20 277 sw t1, 0(t0) 278 279 li t0, MEM_STADDR2 280 li t1, 0x10c03f00 281 sw t1, 0(t0) 282#else 283 li t0, MEM_STCFG2 284 li t1, 0x00000000 285 sw t1, 0(t0) 286 287 li t0, MEM_STTIME2 288 li t1, 0x00000000 289 sw t1, 0(t0) 290 291 li t0, MEM_STADDR2 292 li t1, 0x00000000 293 sw t1, 0(t0) 294#endif 295 296 /* RCE3 PCMCIA 250ns */ 297 li t0, MEM_STCFG3 298 li t1, 0x00000002 299 sw t1, 0(t0) 300 301 li t0, MEM_STTIME3 302 li t1, 0x280E3E07 303 sw t1, 0(t0) 304 305 li t0, MEM_STADDR3 306 li t1, 0x10000000 307 sw t1, 0(t0) 308 309 sync 310 311 /* Set peripherals to a known state */ 312 li t0, IC0_CFG0CLR 313 li t1, 0xFFFFFFFF 314 sw t1, 0(t0) 315 316 li t0, IC0_CFG0CLR 317 sw t1, 0(t0) 318 319 li t0, IC0_CFG1CLR 320 sw t1, 0(t0) 321 322 li t0, IC0_CFG2CLR 323 sw t1, 0(t0) 324 325 li t0, IC0_SRCSET 326 sw t1, 0(t0) 327 328 li t0, IC0_ASSIGNSET 329 sw t1, 0(t0) 330 331 li t0, IC0_WAKECLR 332 sw t1, 0(t0) 333 334 li t0, IC0_RISINGCLR 335 sw t1, 0(t0) 336 337 li t0, IC0_FALLINGCLR 338 sw t1, 0(t0) 339 340 li t0, IC0_TESTBIT 341 li t1, 0x00000000 342 sw t1, 0(t0) 343 sync 344 345 li t0, IC1_CFG0CLR 346 li t1, 0xFFFFFFFF 347 sw t1, 0(t0) 348 349 li t0, IC1_CFG0CLR 350 sw t1, 0(t0) 351 352 li t0, IC1_CFG1CLR 353 sw t1, 0(t0) 354 355 li t0, IC1_CFG2CLR 356 sw t1, 0(t0) 357 358 li t0, IC1_SRCSET 359 sw t1, 0(t0) 360 361 li t0, IC1_ASSIGNSET 362 sw t1, 0(t0) 363 364 li t0, IC1_WAKECLR 365 sw t1, 0(t0) 366 367 li t0, IC1_RISINGCLR 368 sw t1, 0(t0) 369 370 li t0, IC1_FALLINGCLR 371 sw t1, 0(t0) 372 373 li t0, IC1_TESTBIT 374 li t1, 0x00000000 375 sw t1, 0(t0) 376 sync 377 378 li t0, SYS_FREQCTRL0 379 li t1, 0x00000000 380 sw t1, 0(t0) 381 382 li t0, SYS_FREQCTRL1 383 li t1, 0x00000000 384 sw t1, 0(t0) 385 386 li t0, SYS_CLKSRC 387 li t1, 0x00000000 388 sw t1, 0(t0) 389 390 li t0, SYS_PININPUTEN 391 li t1, 0x00000000 392 sw t1, 0(t0) 393 sync 394 395 li t0, 0xB1100100 396 li t1, 0x00000000 397 sw t1, 0(t0) 398 399 li t0, 0xB1400100 400 li t1, 0x00000000 401 sw t1, 0(t0) 402 403 404 li t0, SYS_WAKEMSK 405 li t1, 0x00000000 406 sw t1, 0(t0) 407 408 li t0, SYS_WAKESRC 409 li t1, 0x00000000 410 sw t1, 0(t0) 411 412 /* wait 1mS before setup */ 413 li t1, MEM_1MS 4141: add t1, -1 415 bne t1, zero, 1b 416 nop 417 418#ifdef CONFIG_DBAU1550 419/* SDCS 0,1,2 DDR SDRAM */ 420 li t0, MEM_SDMODE0 421 li t1, 0x04276221 422 sw t1, 0(t0) 423 424 li t0, MEM_SDMODE1 425 li t1, 0x04276221 426 sw t1, 0(t0) 427 428 li t0, MEM_SDMODE2 429 li t1, 0x04276221 430 sw t1, 0(t0) 431 432 li t0, MEM_SDADDR0 433 li t1, 0xe21003f0 434 sw t1, 0(t0) 435 436 li t0, MEM_SDADDR1 437 li t1, 0xe21043f0 438 sw t1, 0(t0) 439 440 li t0, MEM_SDADDR2 441 li t1, 0xe21083f0 442 sw t1, 0(t0) 443 444 sync 445 446 li t0, MEM_SDCONFIGA 447 li t1, 0x9030060a /* Program refresh - disabled */ 448 sw t1, 0(t0) 449 sync 450 451 li t0, MEM_SDCONFIGB 452 li t1, 0x00028000 453 sw t1, 0(t0) 454 sync 455 456 li t0, MEM_SDPRECMD /* Precharge all */ 457 li t1, 0 458 sw t1, 0(t0) 459 sync 460 461 li t0, MEM_SDWRMD0 462 li t1, 0x40000000 463 sw t1, 0(t0) 464 sync 465 466 li t0, MEM_SDWRMD1 467 li t1, 0x40000000 468 sw t1, 0(t0) 469 sync 470 471 li t0, MEM_SDWRMD2 472 li t1, 0x40000000 473 sw t1, 0(t0) 474 sync 475 476 li t0, MEM_SDWRMD0 477 li t1, 0x00000063 478 sw t1, 0(t0) 479 sync 480 481 li t0, MEM_SDWRMD1 482 li t1, 0x00000063 483 sw t1, 0(t0) 484 sync 485 486 li t0, MEM_SDWRMD2 487 li t1, 0x00000063 488 sw t1, 0(t0) 489 sync 490 491 li t0, MEM_SDPRECMD /* Precharge all */ 492 sw zero, 0(t0) 493 sync 494 495 /* Issue 2 autoref */ 496 li t0, MEM_SDAUTOREF 497 sw zero, 0(t0) 498 sync 499 500 li t0, MEM_SDAUTOREF 501 sw zero, 0(t0) 502 sync 503 504 /* Enable refresh */ 505 li t0, MEM_SDCONFIGA 506 li t1, 0x9830060a /* Program refresh - enabled */ 507 sw t1, 0(t0) 508 sync 509 510#else /* CONFIG_DBAU1550 */ 511/* SDCS 0,1 SDRAM */ 512 li t0, MEM_SDMODE0 513 li t1, 0x005522AA 514 sw t1, 0(t0) 515 516 li t0, MEM_SDMODE1 517 li t1, 0x005522AA 518 sw t1, 0(t0) 519 520 li t0, MEM_SDMODE2 521 li t1, 0x00000000 522 sw t1, 0(t0) 523 524 li t0, MEM_SDADDR0 525 li t1, 0x001003F8 526 sw t1, 0(t0) 527 528 529 li t0, MEM_SDADDR1 530 li t1, 0x001023F8 531 sw t1, 0(t0) 532 533 li t0, MEM_SDADDR2 534 li t1, 0x00000000 535 sw t1, 0(t0) 536 537 sync 538 539 li t0, MEM_SDREFCFG 540 li t1, 0x64000C24 /* Disable */ 541 sw t1, 0(t0) 542 sync 543 544 li t0, MEM_SDPRECMD 545 sw zero, 0(t0) 546 sync 547 548 li t0, MEM_SDAUTOREF 549 sw zero, 0(t0) 550 sync 551 sw zero, 0(t0) 552 sync 553 554 li t0, MEM_SDREFCFG 555 li t1, 0x66000C24 /* Enable */ 556 sw t1, 0(t0) 557 sync 558 559 li t0, MEM_SDWRMD0 560 li t1, 0x00000033 561 sw t1, 0(t0) 562 sync 563 564 li t0, MEM_SDWRMD1 565 li t1, 0x00000033 566 sw t1, 0(t0) 567 sync 568 569#endif /* CONFIG_DBAU1550 */ 570 /* wait 1mS after setup */ 571 li t1, MEM_1MS 5721: add t1, -1 573 bne t1, zero, 1b 574 nop 575 576 li t0, SYS_PINFUNC 577 li t1, 0x00008080 578 sw t1, 0(t0) 579 580 li t0, SYS_TRIOUTCLR 581 li t1, 0x00001FFF 582 sw t1, 0(t0) 583 584 li t0, SYS_OUTPUTCLR 585 li t1, 0x00008000 586 sw t1, 0(t0) 587 sync 588 589 j ra 590 nop 591