1/* Memory sub-system initialization code */ 2 3#include <config.h> 4#include <version.h> 5#include <asm/regdef.h> 6#include <asm/au1x00.h> 7#include <asm/mipsregs.h> 8 9#define AU1500_SYS_ADDR 0xB1900000 10#define sys_endian 0x0038 11#define CP0_Config0 $16 12#define CPU_SCALE ((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */ 13#define MEM_1MS ((CFG_MHZ) * 1000) 14 15 .text 16 .set noreorder 17 .set mips32 18 19 .globl lowlevel_init 20lowlevel_init: 21 /* 22 * Step 1) Establish CPU endian mode. 23 * Db1500-specific: 24 * Switch S1.1 Off(bit7 reads 1) is Little Endian 25 * Switch S1.1 On (bit7 reads 0) is Big Endian 26 */ 27#ifdef CONFIG_DBAU1550 28 li t0, MEM_STCFG2 29 li t1, 0x00000040 30 sw t1, 0(t0) 31 32 li t0, MEM_STTIME2 33 li t1, 0x22080a20 34 sw t1, 0(t0) 35 36 li t0, MEM_STADDR2 37 li t1, 0x10c03f00 38 sw t1, 0(t0) 39#else 40 li t0, MEM_STCFG1 41 li t1, 0x00000080 42 sw t1, 0(t0) 43 44 li t0, MEM_STTIME1 45 li t1, 0x22080a20 46 sw t1, 0(t0) 47 48 li t0, MEM_STADDR1 49 li t1, 0x10c03f00 50 sw t1, 0(t0) 51#endif 52 53 li t0, DB1XX0_BCSR_ADDR 54 lw t1,8(t0) 55 andi t1,t1,0x80 56 beq zero,t1,big_endian 57 nop 58little_endian: 59 60 /* Change Au1 core to little endian */ 61 li t0, AU1500_SYS_ADDR 62 li t1, 1 63 sw t1, sys_endian(t0) 64 mfc0 t2, CP0_CONFIG 65 mtc0 t2, CP0_CONFIG 66 nop 67 nop 68 69 /* Big Endian is default so nothing to do but fall through */ 70 71big_endian: 72 73 /* 74 * Step 2) Establish Status Register 75 * (set BEV, clear ERL, clear EXL, clear IE) 76 */ 77 li t1, 0x00400000 78 mtc0 t1, CP0_STATUS 79 80 /* 81 * Step 3) Establish CP0 Config0 82 * (set OD, set K0=3) 83 */ 84 li t1, 0x00080003 85 mtc0 t1, CP0_CONFIG 86 87 /* 88 * Step 4) Disable Watchpoint facilities 89 */ 90 li t1, 0x00000000 91 mtc0 t1, CP0_WATCHLO 92 mtc0 t1, CP0_IWATCHLO 93 /* 94 * Step 5) Disable the performance counters 95 */ 96 mtc0 zero, CP0_PERFORMANCE 97 nop 98 99 /* 100 * Step 6) Establish EJTAG Debug register 101 */ 102 mtc0 zero, CP0_DEBUG 103 nop 104 105 /* 106 * Step 7) Establish Cause 107 * (set IV bit) 108 */ 109 li t1, 0x00800000 110 mtc0 t1, CP0_CAUSE 111 112 /* Establish Wired (and Random) */ 113 mtc0 zero, CP0_WIRED 114 nop 115 116#ifdef CONFIG_DBAU1550 117 /* No workaround if running from ram */ 118 lui t0, 0xffc0 119 lui t3, 0xbfc0 120 and t1, ra, t0 121 bne t1, t3, noCacheJump 122 nop 123 124 /*** From AMD YAMON ***/ 125 /* 126 * Step 8) Initialize the caches 127 */ 128 li t0, (16*1024) 129 li t1, 32 130 li t2, 0x80000000 131 addu t3, t0, t2 132cacheloop: 133 cache 0, 0(t2) 134 cache 1, 0(t2) 135 addu t2, t1 136 bne t2, t3, cacheloop 137 nop 138 139 /* Save return address */ 140 move t3, ra 141 142 /* Run from cacheable space now */ 143 bal cachehere 144 nop 145cachehere: 146 li t1, ~0x20000000 /* convert to KSEG0 */ 147 and t0, ra, t1 148 addi t0, 5*4 /* 5 insns beyond cachehere */ 149 jr t0 150 nop 151 152 /* Restore return address */ 153 move ra, t3 154 155 /* 156 * Step 9) Initialize the TLB 157 */ 158 li t0, 0 # index value 159 li t1, 0x00000000 # entryhi value 160 li t2, 32 # 32 entries 161 162tlbloop: 163 /* Probe TLB for matching EntryHi */ 164 mtc0 t1, CP0_ENTRYHI 165 tlbp 166 nop 167 168 /* Examine Index[P], 1=no matching entry */ 169 mfc0 t3, CP0_INDEX 170 li t4, 0x80000000 171 and t3, t4, t3 172 addiu t1, t1, 1 # increment t1 (asid) 173 beq zero, t3, tlbloop 174 nop 175 176 /* Initialize the TLB entry */ 177 mtc0 t0, CP0_INDEX 178 mtc0 zero, CP0_ENTRYLO0 179 mtc0 zero, CP0_ENTRYLO1 180 mtc0 zero, CP0_PAGEMASK 181 tlbwi 182 183 /* Do it again */ 184 addiu t0, t0, 1 185 bne t0, t2, tlbloop 186 nop 187 188 /* First setup pll:s to make serial work ok */ 189 /* We have a 12 MHz crystal */ 190 li t0, SYS_CPUPLL 191 li t1, CPU_SCALE /* CPU clock */ 192 sw t1, 0(t0) 193 sync 194 nop 195 nop 196 197 /* wait 1mS for clocks to settle */ 198 li t1, MEM_1MS 1991: add t1, -1 200 bne t1, zero, 1b 201 nop 202 /* Setup AUX PLL */ 203 li t0, SYS_AUXPLL 204 li t1, 0x20 /* 96 MHz */ 205 sw t1, 0(t0) /* aux pll */ 206 sync 207 208 /* Static memory controller */ 209 /* RCE0 - can not change while fetching, do so from icache */ 210 move t2, ra /* Store return address */ 211 bal getAddr 212 nop 213 214getAddr: 215 move t1, ra 216 move ra, t2 /* Move return addess back */ 217 218 cache 0x14,0(t1) 219 cache 0x14,32(t1) 220 /*** /From YAMON ***/ 221 222noCacheJump: 223#endif /* CONFIG_DBAU1550 */ 224 225#ifdef CONFIG_DBAU1550 226 li t0, MEM_STTIME0 227 li t1, 0x040181D7 228 sw t1, 0(t0) 229 230 /* RCE0 AMD MirrorBit Flash (?) */ 231 li t0, MEM_STCFG0 232 li t1, 0x00000003 233 sw t1, 0(t0) 234 235 li t0, MEM_STADDR0 236 li t1, 0x11803E00 237 sw t1, 0(t0) 238#else /* CONFIG_DBAU1550 */ 239 li t0, MEM_STTIME0 240 li t1, 0x00014C0F 241 sw t1, 0(t0) 242 243 /* RCE0 AMD 29LV640M MirrorBit Flash */ 244 li t0, MEM_STCFG0 245 li t1, 0x00000013 246 sw t1, 0(t0) 247 248 li t0, MEM_STADDR0 249 li t1, 0x11E03F80 250 sw t1, 0(t0) 251#endif /* CONFIG_DBAU1550 */ 252 253 /* RCE1 CPLD Board Logic */ 254 li t0, MEM_STCFG1 255 li t1, 0x00000080 256 sw t1, 0(t0) 257 258 li t0, MEM_STTIME1 259 li t1, 0x22080a20 260 sw t1, 0(t0) 261 262 li t0, MEM_STADDR1 263 li t1, 0x10c03f00 264 sw t1, 0(t0) 265 266#ifdef CONFIG_DBAU1550 267 /* RCE2 CPLD Board Logic */ 268 li t0, MEM_STCFG2 269 li t1, 0x00000040 270 sw t1, 0(t0) 271 272 li t0, MEM_STTIME2 273 li t1, 0x22080a20 274 sw t1, 0(t0) 275 276 li t0, MEM_STADDR2 277 li t1, 0x10c03f00 278 sw t1, 0(t0) 279#else 280 li t0, MEM_STCFG2 281 li t1, 0x00000000 282 sw t1, 0(t0) 283 284 li t0, MEM_STTIME2 285 li t1, 0x00000000 286 sw t1, 0(t0) 287 288 li t0, MEM_STADDR2 289 li t1, 0x00000000 290 sw t1, 0(t0) 291#endif 292 293 /* RCE3 PCMCIA 250ns */ 294 li t0, MEM_STCFG3 295 li t1, 0x00000002 296 sw t1, 0(t0) 297 298 li t0, MEM_STTIME3 299 li t1, 0x280E3E07 300 sw t1, 0(t0) 301 302 li t0, MEM_STADDR3 303 li t1, 0x10000000 304 sw t1, 0(t0) 305 306 sync 307 308 /* Set peripherals to a known state */ 309 li t0, IC0_CFG0CLR 310 li t1, 0xFFFFFFFF 311 sw t1, 0(t0) 312 313 li t0, IC0_CFG0CLR 314 sw t1, 0(t0) 315 316 li t0, IC0_CFG1CLR 317 sw t1, 0(t0) 318 319 li t0, IC0_CFG2CLR 320 sw t1, 0(t0) 321 322 li t0, IC0_SRCSET 323 sw t1, 0(t0) 324 325 li t0, IC0_ASSIGNSET 326 sw t1, 0(t0) 327 328 li t0, IC0_WAKECLR 329 sw t1, 0(t0) 330 331 li t0, IC0_RISINGCLR 332 sw t1, 0(t0) 333 334 li t0, IC0_FALLINGCLR 335 sw t1, 0(t0) 336 337 li t0, IC0_TESTBIT 338 li t1, 0x00000000 339 sw t1, 0(t0) 340 sync 341 342 li t0, IC1_CFG0CLR 343 li t1, 0xFFFFFFFF 344 sw t1, 0(t0) 345 346 li t0, IC1_CFG0CLR 347 sw t1, 0(t0) 348 349 li t0, IC1_CFG1CLR 350 sw t1, 0(t0) 351 352 li t0, IC1_CFG2CLR 353 sw t1, 0(t0) 354 355 li t0, IC1_SRCSET 356 sw t1, 0(t0) 357 358 li t0, IC1_ASSIGNSET 359 sw t1, 0(t0) 360 361 li t0, IC1_WAKECLR 362 sw t1, 0(t0) 363 364 li t0, IC1_RISINGCLR 365 sw t1, 0(t0) 366 367 li t0, IC1_FALLINGCLR 368 sw t1, 0(t0) 369 370 li t0, IC1_TESTBIT 371 li t1, 0x00000000 372 sw t1, 0(t0) 373 sync 374 375 li t0, SYS_FREQCTRL0 376 li t1, 0x00000000 377 sw t1, 0(t0) 378 379 li t0, SYS_FREQCTRL1 380 li t1, 0x00000000 381 sw t1, 0(t0) 382 383 li t0, SYS_CLKSRC 384 li t1, 0x00000000 385 sw t1, 0(t0) 386 387 li t0, SYS_PININPUTEN 388 li t1, 0x00000000 389 sw t1, 0(t0) 390 sync 391 392 li t0, 0xB1100100 393 li t1, 0x00000000 394 sw t1, 0(t0) 395 396 li t0, 0xB1400100 397 li t1, 0x00000000 398 sw t1, 0(t0) 399 400 401 li t0, SYS_WAKEMSK 402 li t1, 0x00000000 403 sw t1, 0(t0) 404 405 li t0, SYS_WAKESRC 406 li t1, 0x00000000 407 sw t1, 0(t0) 408 409 /* wait 1mS before setup */ 410 li t1, MEM_1MS 4111: add t1, -1 412 bne t1, zero, 1b 413 nop 414 415#ifdef CONFIG_DBAU1550 416/* SDCS 0,1,2 DDR SDRAM */ 417 li t0, MEM_SDMODE0 418 li t1, 0x04276221 419 sw t1, 0(t0) 420 421 li t0, MEM_SDMODE1 422 li t1, 0x04276221 423 sw t1, 0(t0) 424 425 li t0, MEM_SDMODE2 426 li t1, 0x04276221 427 sw t1, 0(t0) 428 429 li t0, MEM_SDADDR0 430 li t1, 0xe21003f0 431 sw t1, 0(t0) 432 433 li t0, MEM_SDADDR1 434 li t1, 0xe21043f0 435 sw t1, 0(t0) 436 437 li t0, MEM_SDADDR2 438 li t1, 0xe21083f0 439 sw t1, 0(t0) 440 441 sync 442 443 li t0, MEM_SDCONFIGA 444 li t1, 0x9030060a /* Program refresh - disabled */ 445 sw t1, 0(t0) 446 sync 447 448 li t0, MEM_SDCONFIGB 449 li t1, 0x00028000 450 sw t1, 0(t0) 451 sync 452 453 li t0, MEM_SDPRECMD /* Precharge all */ 454 li t1, 0 455 sw t1, 0(t0) 456 sync 457 458 li t0, MEM_SDWRMD0 459 li t1, 0x40000000 460 sw t1, 0(t0) 461 sync 462 463 li t0, MEM_SDWRMD1 464 li t1, 0x40000000 465 sw t1, 0(t0) 466 sync 467 468 li t0, MEM_SDWRMD2 469 li t1, 0x40000000 470 sw t1, 0(t0) 471 sync 472 473 li t0, MEM_SDWRMD0 474 li t1, 0x00000063 475 sw t1, 0(t0) 476 sync 477 478 li t0, MEM_SDWRMD1 479 li t1, 0x00000063 480 sw t1, 0(t0) 481 sync 482 483 li t0, MEM_SDWRMD2 484 li t1, 0x00000063 485 sw t1, 0(t0) 486 sync 487 488 li t0, MEM_SDPRECMD /* Precharge all */ 489 sw zero, 0(t0) 490 sync 491 492 /* Issue 2 autoref */ 493 li t0, MEM_SDAUTOREF 494 sw zero, 0(t0) 495 sync 496 497 li t0, MEM_SDAUTOREF 498 sw zero, 0(t0) 499 sync 500 501 /* Enable refresh */ 502 li t0, MEM_SDCONFIGA 503 li t1, 0x9830060a /* Program refresh - enabled */ 504 sw t1, 0(t0) 505 sync 506 507#else /* CONFIG_DBAU1550 */ 508/* SDCS 0,1 SDRAM */ 509 li t0, MEM_SDMODE0 510 li t1, 0x005522AA 511 sw t1, 0(t0) 512 513 li t0, MEM_SDMODE1 514 li t1, 0x005522AA 515 sw t1, 0(t0) 516 517 li t0, MEM_SDMODE2 518 li t1, 0x00000000 519 sw t1, 0(t0) 520 521 li t0, MEM_SDADDR0 522 li t1, 0x001003F8 523 sw t1, 0(t0) 524 525 526 li t0, MEM_SDADDR1 527 li t1, 0x001023F8 528 sw t1, 0(t0) 529 530 li t0, MEM_SDADDR2 531 li t1, 0x00000000 532 sw t1, 0(t0) 533 534 sync 535 536 li t0, MEM_SDREFCFG 537 li t1, 0x64000C24 /* Disable */ 538 sw t1, 0(t0) 539 sync 540 541 li t0, MEM_SDPRECMD 542 sw zero, 0(t0) 543 sync 544 545 li t0, MEM_SDAUTOREF 546 sw zero, 0(t0) 547 sync 548 sw zero, 0(t0) 549 sync 550 551 li t0, MEM_SDREFCFG 552 li t1, 0x66000C24 /* Enable */ 553 sw t1, 0(t0) 554 sync 555 556 li t0, MEM_SDWRMD0 557 li t1, 0x00000033 558 sw t1, 0(t0) 559 sync 560 561 li t0, MEM_SDWRMD1 562 li t1, 0x00000033 563 sw t1, 0(t0) 564 sync 565 566#endif /* CONFIG_DBAU1550 */ 567 /* wait 1mS after setup */ 568 li t1, MEM_1MS 5691: add t1, -1 570 bne t1, zero, 1b 571 nop 572 573 li t0, SYS_PINFUNC 574 li t1, 0x00008080 575 sw t1, 0(t0) 576 577 li t0, SYS_TRIOUTCLR 578 li t1, 0x00001FFF 579 sw t1, 0(t0) 580 581 li t0, SYS_OUTPUTCLR 582 li t1, 0x00008000 583 sw t1, 0(t0) 584 sync 585 586 j ra 587 nop 588