1 /* 2 * (C) Copyright 2003 3 * Thomas.Lange@corelatus.se 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <command.h> 26 #include <asm/au1x00.h> 27 #include <asm/mipsregs.h> 28 #include <asm/io.h> 29 30 phys_size_t initdram(int board_type) 31 { 32 /* Sdram is setup by assembler code */ 33 /* If memory could be changed, we should return the true value here */ 34 return MEM_SIZE*1024*1024; 35 } 36 37 #define BCSR_PCMCIA_PC0DRVEN 0x0010 38 #define BCSR_PCMCIA_PC0RST 0x0080 39 40 /* In cpu/mips/cpu.c */ 41 void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); 42 43 int checkboard (void) 44 { 45 #ifdef CONFIG_IDE_PCMCIA 46 u16 status; 47 volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10); 48 #endif /* CONFIG_IDE_PCMCIA */ 49 volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC); 50 volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; 51 u32 proc_id; 52 53 *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ 54 55 proc_id = read_c0_prid(); 56 57 switch (proc_id >> 24) { 58 case 0: 59 puts ("Board: Merlot (DbAu1000)\n"); 60 printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", 61 (proc_id >> 8) & 0xFF, proc_id & 0xFF); 62 break; 63 case 1: 64 puts ("Board: DbAu1500\n"); 65 printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n", 66 (proc_id >> 8) & 0xFF, proc_id & 0xFF); 67 break; 68 case 2: 69 puts ("Board: DbAu1100\n"); 70 printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n", 71 (proc_id >> 8) & 0xFF, proc_id & 0xFF); 72 break; 73 case 3: 74 puts ("Board: DbAu1550\n"); 75 printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n", 76 (proc_id >> 8) & 0xFF, proc_id & 0xFF); 77 break; 78 default: 79 printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); 80 } 81 82 set_io_port_base(0); 83 84 #ifdef CONFIG_IDE_PCMCIA 85 /* Enable 3.3 V on slot 0 ( VCC ) 86 No 5V */ 87 status = 4; 88 *pcmcia_bcsr = status; 89 90 status |= BCSR_PCMCIA_PC0DRVEN; 91 *pcmcia_bcsr = status; 92 au_sync(); 93 94 udelay(300*1000); 95 96 status |= BCSR_PCMCIA_PC0RST; 97 *pcmcia_bcsr = status; 98 au_sync(); 99 100 udelay(100*1000); 101 102 /* PCMCIA is on a 36 bit physical address. 103 We need to map it into a 32 bit addresses */ 104 105 #if 0 106 /* We dont need theese unless we run whole pcmcia package */ 107 write_one_tlb(20, /* index */ 108 0x01ffe000, /* Pagemask, 16 MB pages */ 109 CFG_PCMCIA_IO_BASE, /* Hi */ 110 0x3C000017, /* Lo0 */ 111 0x3C200017); /* Lo1 */ 112 113 write_one_tlb(21, /* index */ 114 0x01ffe000, /* Pagemask, 16 MB pages */ 115 CFG_PCMCIA_ATTR_BASE, /* Hi */ 116 0x3D000017, /* Lo0 */ 117 0x3D200017); /* Lo1 */ 118 #endif /* 0 */ 119 write_one_tlb(22, /* index */ 120 0x01ffe000, /* Pagemask, 16 MB pages */ 121 CFG_PCMCIA_MEM_ADDR, /* Hi */ 122 0x3E000017, /* Lo0 */ 123 0x3E200017); /* Lo1 */ 124 #endif /* CONFIG_IDE_PCMCIA */ 125 126 /* Release reset of ethernet PHY chips */ 127 /* Always do this, because linux does not know about it */ 128 *phy = 3; 129 130 return 0; 131 } 132