1 /* 2 * (C) Copyright 2010 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de 4 * 5 * Based on da850evm.c, original Copyrights follow: 6 * 7 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 8 * 9 * Based on da830evm.c. Original Copyrights follow: 10 * 11 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 12 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 27 */ 28 29 #include <common.h> 30 #include <i2c.h> 31 #include <net.h> 32 #include <netdev.h> 33 #include <asm/arch/hardware.h> 34 #include <asm/arch/emif_defs.h> 35 #include <asm/arch/emac_defs.h> 36 #include <asm/io.h> 37 #include <asm/arch/davinci_misc.h> 38 #include <asm/arch/gpio.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) 43 44 /* SPI0 pin muxer settings */ 45 static const struct pinmux_config spi1_pins[] = { 46 { pinmux(5), 1, 1 }, 47 { pinmux(5), 1, 2 }, 48 { pinmux(5), 1, 4 }, 49 { pinmux(5), 1, 5 } 50 }; 51 52 /* UART0 pin muxer settings */ 53 static const struct pinmux_config uart_pins[] = { 54 { pinmux(3), 2, 7 }, 55 { pinmux(3), 2, 6 }, 56 { pinmux(3), 2, 4 }, 57 { pinmux(3), 2, 5 } 58 }; 59 60 #ifdef CONFIG_DRIVER_TI_EMAC 61 #define HAS_RMII 1 62 static const struct pinmux_config emac_pins[] = { 63 { pinmux(14), 8, 2 }, 64 { pinmux(14), 8, 3 }, 65 { pinmux(14), 8, 4 }, 66 { pinmux(14), 8, 5 }, 67 { pinmux(14), 8, 6 }, 68 { pinmux(14), 8, 7 }, 69 { pinmux(15), 8, 1 }, 70 { pinmux(4), 8, 0 }, 71 { pinmux(4), 8, 1 } 72 }; 73 #endif 74 75 #ifdef CONFIG_NAND_DAVINCI 76 const struct pinmux_config nand_pins[] = { 77 { pinmux(7), 1, 0}, /* CS2 */ 78 { pinmux(7), 0, 1}, /* CS3 in three state*/ 79 { pinmux(7), 1, 4 }, /* EMA_WE */ 80 { pinmux(7), 1, 5 }, /* EMA_OE */ 81 { pinmux(9), 1, 0 }, /* EMA_D[7] */ 82 { pinmux(9), 1, 1 }, /* EMA_D[6] */ 83 { pinmux(9), 1, 2 }, /* EMA_D[5] */ 84 { pinmux(9), 1, 3 }, /* EMA_D[4] */ 85 { pinmux(9), 1, 4 }, /* EMA_D[3] */ 86 { pinmux(9), 1, 5 }, /* EMA_D[2] */ 87 { pinmux(9), 1, 6 }, /* EMA_D[1] */ 88 { pinmux(9), 1, 7 }, /* EMA_D[0] */ 89 { pinmux(12), 1, 5 }, /* EMA_A[2] */ 90 { pinmux(12), 1, 6 }, /* EMA_A[1] */ 91 { pinmux(6), 1, 0 } /* EMA_CLK */ 92 }; 93 #endif 94 95 const struct pinmux_config gpio_pins[] = { 96 { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/ 97 { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/ 98 { pinmux(13), 8, 3 } /* GPIO6[12] U0_SW1 on EA20-00101_2*/ 99 }; 100 101 const struct pinmux_config halten_pin[] = { 102 { pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */ 103 }; 104 105 static const struct pinmux_resource pinmuxes[] = { 106 #ifdef CONFIG_SPI_FLASH 107 PINMUX_ITEM(spi1_pins), 108 #endif 109 PINMUX_ITEM(uart_pins), 110 #ifdef CONFIG_NAND_DAVINCI 111 PINMUX_ITEM(nand_pins), 112 #endif 113 }; 114 115 static const struct lpsc_resource lpsc[] = { 116 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ 117 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ 118 { DAVINCI_LPSC_EMAC }, /* image download */ 119 { DAVINCI_LPSC_UART0 }, /* console */ 120 { DAVINCI_LPSC_GPIO }, 121 }; 122 123 int board_early_init_f(void) 124 { 125 struct davinci_gpio *gpio6_base = 126 (struct davinci_gpio *)DAVINCI_GPIO_BANK67; 127 128 /* PinMux for GPIO */ 129 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) 130 return 1; 131 132 /* Set the RESETOUTn low */ 133 writel((readl(&gpio6_base->set_data) & ~(1 << 15)), 134 &gpio6_base->set_data); 135 writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir); 136 137 /* Set U0_SW0 low for UART0 as console*/ 138 writel((readl(&gpio6_base->set_data) & ~(1 << 10)), 139 &gpio6_base->set_data); 140 writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir); 141 142 /* Set U0_SW1 low for UART0 as console*/ 143 writel((readl(&gpio6_base->set_data) & ~(1 << 12)), 144 &gpio6_base->set_data); 145 writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir); 146 147 #ifndef CONFIG_USE_IRQ 148 irq_init(); 149 #endif 150 151 /* 152 * NAND CS setup - cycle counts based on da850evm NAND timings in the 153 * Linux kernel @ 25MHz EMIFA 154 */ 155 #ifdef CONFIG_NAND_DAVINCI 156 writel((DAVINCI_ABCR_WSETUP(0) | 157 DAVINCI_ABCR_WSTROBE(1) | 158 DAVINCI_ABCR_WHOLD(0) | 159 DAVINCI_ABCR_RSETUP(0) | 160 DAVINCI_ABCR_RSTROBE(1) | 161 DAVINCI_ABCR_RHOLD(0) | 162 DAVINCI_ABCR_TA(0) | 163 DAVINCI_ABCR_ASIZE_8BIT), 164 &davinci_emif_regs->ab1cr); /* CS2 */ 165 #endif 166 167 /* 168 * Power on required peripherals 169 * ARM does not have access by default to PSC0 and PSC1 170 * assuming here that the DSP bootloader has set the IOPU 171 * such that PSC access is available to ARM 172 */ 173 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 174 return 1; 175 176 /* setup the SUSPSRC for ARM to control emulation suspend */ 177 writel(readl(&davinci_syscfg_regs->suspsrc) & 178 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | 179 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | 180 DAVINCI_SYSCFG_SUSPSRC_UART0), 181 &davinci_syscfg_regs->suspsrc); 182 183 /* configure pinmux settings */ 184 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) 185 return 1; 186 187 #ifdef CONFIG_DRIVER_TI_EMAC 188 if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) 189 return 1; 190 191 davinci_emac_mii_mode_sel(HAS_RMII); 192 #endif /* CONFIG_DRIVER_TI_EMAC */ 193 194 /* enable the console UART */ 195 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 196 DAVINCI_UART_PWREMU_MGMT_UTRST), 197 &davinci_uart0_ctrl_regs->pwremu_mgmt); 198 199 return 0; 200 } 201 202 int board_init(void) 203 { 204 /* arch number of the board */ 205 gd->bd->bi_arch_number = MACH_TYPE_EA20; 206 207 /* address of boot parameters */ 208 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; 209 210 return 0; 211 } 212 213 #ifdef BOARD_LATE_INIT 214 215 int board_late_init(void) 216 { 217 struct davinci_gpio *gpio8_base = 218 (struct davinci_gpio *)DAVINCI_GPIO_BANK8; 219 220 /* PinMux for HALTEN */ 221 if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0) 222 return 1; 223 224 /* Set HALTEN to high */ 225 writel((readl(&gpio8_base->set_data) | (1 << 6)), 226 &gpio8_base->set_data); 227 writel((readl(&gpio8_base->dir) & ~(1 << 6)), &gpio8_base->dir); 228 229 return 0; 230 } 231 #endif /* BOARD_LATE_INIT */ 232 233 #ifdef CONFIG_DRIVER_TI_EMAC 234 235 /* 236 * Initializes on-board ethernet controllers. 237 */ 238 int board_eth_init(bd_t *bis) 239 { 240 if (!davinci_emac_initialize()) { 241 printf("Error: Ethernet init failed!\n"); 242 return -1; 243 } 244 245 /* 246 * This board has a RMII PHY. However, the MDC line on the SOM 247 * must not be disabled (there is no MII PHY on the 248 * baseboard) via the GPIO2[6], because this pin 249 * disables at the same time the SPI flash. 250 */ 251 252 return 0; 253 } 254 #endif /* CONFIG_DRIVER_TI_EMAC */ 255