1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on da830evm.c. Original Copyrights follow: 5 * 6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #include <common.h> 25 #include <i2c.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <asm/arch/hardware.h> 29 #include <asm/arch/emif_defs.h> 30 #include <asm/arch/emac_defs.h> 31 #include <asm/io.h> 32 #include <asm/arch/davinci_misc.h> 33 #include <hwconfig.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) 38 39 /* SPI0 pin muxer settings */ 40 static const struct pinmux_config spi1_pins[] = { 41 { pinmux(5), 1, 1 }, 42 { pinmux(5), 1, 2 }, 43 { pinmux(5), 1, 4 }, 44 { pinmux(5), 1, 5 } 45 }; 46 47 /* UART pin muxer settings */ 48 static const struct pinmux_config uart_pins[] = { 49 { pinmux(0), 4, 6 }, 50 { pinmux(0), 4, 7 }, 51 { pinmux(4), 2, 4 }, 52 { pinmux(4), 2, 5 } 53 }; 54 55 #ifdef CONFIG_DRIVER_TI_EMAC 56 static const struct pinmux_config emac_pins[] = { 57 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 58 { pinmux(14), 8, 2 }, 59 { pinmux(14), 8, 3 }, 60 { pinmux(14), 8, 4 }, 61 { pinmux(14), 8, 5 }, 62 { pinmux(14), 8, 6 }, 63 { pinmux(14), 8, 7 }, 64 { pinmux(15), 8, 1 }, 65 #else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */ 66 { pinmux(2), 8, 1 }, 67 { pinmux(2), 8, 2 }, 68 { pinmux(2), 8, 3 }, 69 { pinmux(2), 8, 4 }, 70 { pinmux(2), 8, 5 }, 71 { pinmux(2), 8, 6 }, 72 { pinmux(2), 8, 7 }, 73 { pinmux(3), 8, 0 }, 74 { pinmux(3), 8, 1 }, 75 { pinmux(3), 8, 2 }, 76 { pinmux(3), 8, 3 }, 77 { pinmux(3), 8, 4 }, 78 { pinmux(3), 8, 5 }, 79 { pinmux(3), 8, 6 }, 80 { pinmux(3), 8, 7 }, 81 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ 82 { pinmux(4), 8, 0 }, 83 { pinmux(4), 8, 1 } 84 }; 85 86 /* I2C pin muxer settings */ 87 static const struct pinmux_config i2c_pins[] = { 88 { pinmux(4), 2, 2 }, 89 { pinmux(4), 2, 3 } 90 }; 91 92 #ifdef CONFIG_NAND_DAVINCI 93 const struct pinmux_config nand_pins[] = { 94 { pinmux(7), 1, 1 }, 95 { pinmux(7), 1, 2 }, 96 { pinmux(7), 1, 4 }, 97 { pinmux(7), 1, 5 }, 98 { pinmux(9), 1, 0 }, 99 { pinmux(9), 1, 1 }, 100 { pinmux(9), 1, 2 }, 101 { pinmux(9), 1, 3 }, 102 { pinmux(9), 1, 4 }, 103 { pinmux(9), 1, 5 }, 104 { pinmux(9), 1, 6 }, 105 { pinmux(9), 1, 7 }, 106 { pinmux(12), 1, 5 }, 107 { pinmux(12), 1, 6 } 108 }; 109 #elif defined(CONFIG_USE_NOR) 110 /* NOR pin muxer settings */ 111 const struct pinmux_config nor_pins[] = { 112 { pinmux(5), 1, 6 }, 113 { pinmux(6), 1, 6 }, 114 { pinmux(7), 1, 0 }, 115 { pinmux(7), 1, 4 }, 116 { pinmux(7), 1, 5 }, 117 { pinmux(8), 1, 0 }, 118 { pinmux(8), 1, 1 }, 119 { pinmux(8), 1, 2 }, 120 { pinmux(8), 1, 3 }, 121 { pinmux(8), 1, 4 }, 122 { pinmux(8), 1, 5 }, 123 { pinmux(8), 1, 6 }, 124 { pinmux(8), 1, 7 }, 125 { pinmux(9), 1, 0 }, 126 { pinmux(9), 1, 1 }, 127 { pinmux(9), 1, 2 }, 128 { pinmux(9), 1, 3 }, 129 { pinmux(9), 1, 4 }, 130 { pinmux(9), 1, 5 }, 131 { pinmux(9), 1, 6 }, 132 { pinmux(9), 1, 7 }, 133 { pinmux(10), 1, 0 }, 134 { pinmux(10), 1, 1 }, 135 { pinmux(10), 1, 2 }, 136 { pinmux(10), 1, 3 }, 137 { pinmux(10), 1, 4 }, 138 { pinmux(10), 1, 5 }, 139 { pinmux(10), 1, 6 }, 140 { pinmux(10), 1, 7 }, 141 { pinmux(11), 1, 0 }, 142 { pinmux(11), 1, 1 }, 143 { pinmux(11), 1, 2 }, 144 { pinmux(11), 1, 3 }, 145 { pinmux(11), 1, 4 }, 146 { pinmux(11), 1, 5 }, 147 { pinmux(11), 1, 6 }, 148 { pinmux(11), 1, 7 }, 149 { pinmux(12), 1, 0 }, 150 { pinmux(12), 1, 1 }, 151 { pinmux(12), 1, 2 }, 152 { pinmux(12), 1, 3 }, 153 { pinmux(12), 1, 4 }, 154 { pinmux(12), 1, 5 }, 155 { pinmux(12), 1, 6 }, 156 { pinmux(12), 1, 7 } 157 }; 158 #endif 159 160 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 161 #define HAS_RMII 1 162 #else 163 #define HAS_RMII 0 164 #endif 165 #endif /* CONFIG_DRIVER_TI_EMAC */ 166 167 void dsp_lpsc_on(unsigned domain, unsigned int id) 168 { 169 dv_reg_p mdstat, mdctl, ptstat, ptcmd; 170 struct davinci_psc_regs *psc_regs; 171 172 psc_regs = davinci_psc0_regs; 173 mdstat = &psc_regs->psc0.mdstat[id]; 174 mdctl = &psc_regs->psc0.mdctl[id]; 175 ptstat = &psc_regs->ptstat; 176 ptcmd = &psc_regs->ptcmd; 177 178 while (*ptstat & (0x1 << domain)) 179 ; 180 181 if ((*mdstat & 0x1f) == 0x03) 182 return; /* Already on and enabled */ 183 184 *mdctl |= 0x03; 185 186 *ptcmd = 0x1 << domain; 187 188 while (*ptstat & (0x1 << domain)) 189 ; 190 while ((*mdstat & 0x1f) != 0x03) 191 ; /* Probably an overkill... */ 192 } 193 194 static void dspwake(void) 195 { 196 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; 197 u32 val; 198 199 /* if the device is ARM only, return */ 200 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) 201 return; 202 203 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) 204 return; 205 206 *resetvect++ = 0x1E000; /* DSP Idle */ 207 /* clear out the next 10 words as NOP */ 208 memset(resetvect, 0, sizeof(unsigned) *10); 209 210 /* setup the DSP reset vector */ 211 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); 212 213 dsp_lpsc_on(1, DAVINCI_LPSC_GEM); 214 val = readl(PSC0_MDCTL + (15 * 4)); 215 val |= 0x100; 216 writel(val, (PSC0_MDCTL + (15 * 4))); 217 } 218 219 int misc_init_r(void) 220 { 221 dspwake(); 222 return 0; 223 } 224 225 static const struct pinmux_resource pinmuxes[] = { 226 #ifdef CONFIG_SPI_FLASH 227 PINMUX_ITEM(spi1_pins), 228 #endif 229 PINMUX_ITEM(uart_pins), 230 PINMUX_ITEM(i2c_pins), 231 #ifdef CONFIG_NAND_DAVINCI 232 PINMUX_ITEM(nand_pins), 233 #elif defined(CONFIG_USE_NOR) 234 PINMUX_ITEM(nor_pins), 235 #endif 236 }; 237 238 static const struct lpsc_resource lpsc[] = { 239 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ 240 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ 241 { DAVINCI_LPSC_EMAC }, /* image download */ 242 { DAVINCI_LPSC_UART2 }, /* console */ 243 { DAVINCI_LPSC_GPIO }, 244 }; 245 246 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK 247 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 248 #endif 249 250 /* 251 * get_board_rev() - setup to pass kernel board revision information 252 * Returns: 253 * bit[0-3] Maximum cpu clock rate supported by onboard SoC 254 * 0000b - 300 MHz 255 * 0001b - 372 MHz 256 * 0010b - 408 MHz 257 * 0011b - 456 MHz 258 */ 259 u32 get_board_rev(void) 260 { 261 char *s; 262 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; 263 u32 rev = 0; 264 265 s = getenv("maxcpuclk"); 266 if (s) 267 maxcpuclk = simple_strtoul(s, NULL, 10); 268 269 if (maxcpuclk >= 456000000) 270 rev = 3; 271 else if (maxcpuclk >= 408000000) 272 rev = 2; 273 else if (maxcpuclk >= 372000000) 274 rev = 1; 275 276 return rev; 277 } 278 279 int board_init(void) 280 { 281 #ifndef CONFIG_USE_IRQ 282 irq_init(); 283 #endif 284 285 286 #ifdef CONFIG_NAND_DAVINCI 287 /* 288 * NAND CS setup - cycle counts based on da850evm NAND timings in the 289 * Linux kernel @ 25MHz EMIFA 290 */ 291 writel((DAVINCI_ABCR_WSETUP(0) | 292 DAVINCI_ABCR_WSTROBE(1) | 293 DAVINCI_ABCR_WHOLD(0) | 294 DAVINCI_ABCR_RSETUP(0) | 295 DAVINCI_ABCR_RSTROBE(1) | 296 DAVINCI_ABCR_RHOLD(0) | 297 DAVINCI_ABCR_TA(1) | 298 DAVINCI_ABCR_ASIZE_8BIT), 299 &davinci_emif_regs->ab2cr); /* CS3 */ 300 #endif 301 302 /* arch number of the board */ 303 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; 304 305 /* address of boot parameters */ 306 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; 307 308 /* 309 * Power on required peripherals 310 * ARM does not have access by default to PSC0 and PSC1 311 * assuming here that the DSP bootloader has set the IOPU 312 * such that PSC access is available to ARM 313 */ 314 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 315 return 1; 316 317 /* setup the SUSPSRC for ARM to control emulation suspend */ 318 writel(readl(&davinci_syscfg_regs->suspsrc) & 319 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | 320 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | 321 DAVINCI_SYSCFG_SUSPSRC_UART2), 322 &davinci_syscfg_regs->suspsrc); 323 324 /* configure pinmux settings */ 325 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) 326 return 1; 327 328 #ifdef CONFIG_DRIVER_TI_EMAC 329 if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) 330 return 1; 331 332 davinci_emac_mii_mode_sel(HAS_RMII); 333 #endif /* CONFIG_DRIVER_TI_EMAC */ 334 335 /* enable the console UART */ 336 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 337 DAVINCI_UART_PWREMU_MGMT_UTRST), 338 &davinci_uart2_ctrl_regs->pwremu_mgmt); 339 340 return 0; 341 } 342 343 #ifdef CONFIG_DRIVER_TI_EMAC 344 345 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 346 /** 347 * rmii_hw_init 348 * 349 * DA850/OMAP-L138 EVM can interface to a daughter card for 350 * additional features. This card has an I2C GPIO Expander TCA6416 351 * to select the required functions like camera, RMII Ethernet, 352 * character LCD, video. 353 * 354 * Initialization of the expander involves configuring the 355 * polarity and direction of the ports. P07-P05 are used here. 356 * These ports are connected to a Mux chip which enables only one 357 * functionality at a time. 358 * 359 * For RMII phy to respond, the MII MDIO clock has to be disabled 360 * since both the PHY devices have address as zero. The MII MDIO 361 * clock is controlled via GPIO2[6]. 362 * 363 * This code is valid for Beta version of the hardware 364 */ 365 int rmii_hw_init(void) 366 { 367 const struct pinmux_config gpio_pins[] = { 368 { pinmux(6), 8, 1 } 369 }; 370 u_int8_t buf[2]; 371 unsigned int temp; 372 int ret; 373 374 /* PinMux for GPIO */ 375 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) 376 return 1; 377 378 /* I2C Exapnder configuration */ 379 /* Set polarity to non-inverted */ 380 buf[0] = 0x0; 381 buf[1] = 0x0; 382 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); 383 if (ret) { 384 printf("\nExpander @ 0x%02x write FAILED!!!\n", 385 CONFIG_SYS_I2C_EXPANDER_ADDR); 386 return ret; 387 } 388 389 /* Configure P07-P05 as outputs */ 390 buf[0] = 0x1f; 391 buf[1] = 0xff; 392 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); 393 if (ret) { 394 printf("\nExpander @ 0x%02x write FAILED!!!\n", 395 CONFIG_SYS_I2C_EXPANDER_ADDR); 396 } 397 398 /* For Ethernet RMII selection 399 * P07(SelA)=0 400 * P06(SelB)=1 401 * P05(SelC)=1 402 */ 403 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 404 printf("\nExpander @ 0x%02x read FAILED!!!\n", 405 CONFIG_SYS_I2C_EXPANDER_ADDR); 406 } 407 408 buf[0] &= 0x1f; 409 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); 410 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 411 printf("\nExpander @ 0x%02x write FAILED!!!\n", 412 CONFIG_SYS_I2C_EXPANDER_ADDR); 413 } 414 415 /* Set the output as high */ 416 temp = REG(GPIO_BANK2_REG_SET_ADDR); 417 temp |= (0x01 << 6); 418 REG(GPIO_BANK2_REG_SET_ADDR) = temp; 419 420 /* Set the GPIO direction as output */ 421 temp = REG(GPIO_BANK2_REG_DIR_ADDR); 422 temp &= ~(0x01 << 6); 423 REG(GPIO_BANK2_REG_DIR_ADDR) = temp; 424 425 return 0; 426 } 427 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ 428 429 /* 430 * Initializes on-board ethernet controllers. 431 */ 432 int board_eth_init(bd_t *bis) 433 { 434 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 435 /* Select RMII fucntion through the expander */ 436 if (rmii_hw_init()) 437 printf("RMII hardware init failed!!!\n"); 438 #endif 439 if (!davinci_emac_initialize()) { 440 printf("Error: Ethernet init failed!\n"); 441 return -1; 442 } 443 444 return 0; 445 } 446 #endif /* CONFIG_DRIVER_TI_EMAC */ 447