1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on da830evm.c. Original Copyrights follow: 5 * 6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #include <common.h> 25 #include <i2c.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <spi.h> 29 #include <spi_flash.h> 30 #include <asm/arch/hardware.h> 31 #include <asm/arch/emif_defs.h> 32 #include <asm/arch/emac_defs.h> 33 #include <asm/arch/pinmux_defs.h> 34 #include <asm/io.h> 35 #include <asm/arch/davinci_misc.h> 36 #include <asm/errno.h> 37 #include <hwconfig.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 #ifdef CONFIG_DRIVER_TI_EMAC 42 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 43 #define HAS_RMII 1 44 #else 45 #define HAS_RMII 0 46 #endif 47 #endif /* CONFIG_DRIVER_TI_EMAC */ 48 49 #define CFG_MAC_ADDR_SPI_BUS 0 50 #define CFG_MAC_ADDR_SPI_CS 0 51 #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 52 #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3 53 54 #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) 55 56 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH 57 static int get_mac_addr(u8 *addr) 58 { 59 struct spi_flash *flash; 60 int ret; 61 62 flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS, 63 CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE); 64 if (!flash) { 65 printf("Error - unable to probe SPI flash.\n"); 66 return -1; 67 } 68 69 ret = spi_flash_read(flash, CFG_MAC_ADDR_OFFSET, 6, addr); 70 if (ret) { 71 printf("Error - unable to read MAC address from SPI flash.\n"); 72 return -1; 73 } 74 75 return ret; 76 } 77 #endif 78 79 void dsp_lpsc_on(unsigned domain, unsigned int id) 80 { 81 dv_reg_p mdstat, mdctl, ptstat, ptcmd; 82 struct davinci_psc_regs *psc_regs; 83 84 psc_regs = davinci_psc0_regs; 85 mdstat = &psc_regs->psc0.mdstat[id]; 86 mdctl = &psc_regs->psc0.mdctl[id]; 87 ptstat = &psc_regs->ptstat; 88 ptcmd = &psc_regs->ptcmd; 89 90 while (*ptstat & (0x1 << domain)) 91 ; 92 93 if ((*mdstat & 0x1f) == 0x03) 94 return; /* Already on and enabled */ 95 96 *mdctl |= 0x03; 97 98 *ptcmd = 0x1 << domain; 99 100 while (*ptstat & (0x1 << domain)) 101 ; 102 while ((*mdstat & 0x1f) != 0x03) 103 ; /* Probably an overkill... */ 104 } 105 106 static void dspwake(void) 107 { 108 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; 109 u32 val; 110 111 /* if the device is ARM only, return */ 112 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) 113 return; 114 115 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) 116 return; 117 118 *resetvect++ = 0x1E000; /* DSP Idle */ 119 /* clear out the next 10 words as NOP */ 120 memset(resetvect, 0, sizeof(unsigned) *10); 121 122 /* setup the DSP reset vector */ 123 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); 124 125 dsp_lpsc_on(1, DAVINCI_LPSC_GEM); 126 val = readl(PSC0_MDCTL + (15 * 4)); 127 val |= 0x100; 128 writel(val, (PSC0_MDCTL + (15 * 4))); 129 } 130 131 int misc_init_r(void) 132 { 133 dspwake(); 134 135 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH 136 uchar env_enetaddr[6]; 137 int enetaddr_found; 138 int spi_mac_read; 139 uchar buff[6]; 140 141 enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr); 142 spi_mac_read = get_mac_addr(buff); 143 144 /* 145 * MAC address not present in the environment 146 * try and read the MAC address from SPI flash 147 * and set it. 148 */ 149 if (!enetaddr_found) { 150 if (!spi_mac_read) { 151 if (is_valid_ether_addr(buff)) { 152 if (eth_setenv_enetaddr("ethaddr", buff)) { 153 printf("Warning: Failed to " 154 "set MAC address from SPI flash\n"); 155 } 156 } else { 157 printf("Warning: Invalid " 158 "MAC address read from SPI flash\n"); 159 } 160 } 161 } else { 162 /* 163 * MAC address present in environment compare it with 164 * the MAC address in SPI flash and warn on mismatch 165 */ 166 if (!spi_mac_read && is_valid_ether_addr(buff) && 167 memcmp(env_enetaddr, buff, 6)) 168 printf("Warning: MAC address in SPI flash don't match " 169 "with the MAC address in the environment\n"); 170 printf("Default using MAC address from environment\n"); 171 } 172 #endif 173 return 0; 174 } 175 176 static const struct pinmux_config gpio_pins[] = { 177 #ifdef CONFIG_USE_NOR 178 /* GP0[11] is required for NOR to work on Rev 3 EVMs */ 179 { pinmux(0), 8, 4 }, /* GP0[11] */ 180 #endif 181 }; 182 183 const struct pinmux_resource pinmuxes[] = { 184 #ifdef CONFIG_DRIVER_TI_EMAC 185 PINMUX_ITEM(emac_pins_mdio), 186 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 187 PINMUX_ITEM(emac_pins_rmii), 188 #else 189 PINMUX_ITEM(emac_pins_mii), 190 #endif 191 #endif 192 #ifdef CONFIG_SPI_FLASH 193 PINMUX_ITEM(spi1_pins_base), 194 PINMUX_ITEM(spi1_pins_scs0), 195 #endif 196 PINMUX_ITEM(uart2_pins_txrx), 197 PINMUX_ITEM(uart2_pins_rtscts), 198 PINMUX_ITEM(i2c0_pins), 199 #ifdef CONFIG_NAND_DAVINCI 200 PINMUX_ITEM(emifa_pins_cs3), 201 PINMUX_ITEM(emifa_pins_cs4), 202 PINMUX_ITEM(emifa_pins_nand), 203 #elif defined(CONFIG_USE_NOR) 204 PINMUX_ITEM(emifa_pins_cs2), 205 PINMUX_ITEM(emifa_pins_nor), 206 #endif 207 PINMUX_ITEM(gpio_pins), 208 }; 209 210 const int pinmuxes_size = ARRAY_SIZE(pinmuxes); 211 212 const struct lpsc_resource lpsc[] = { 213 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ 214 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ 215 { DAVINCI_LPSC_EMAC }, /* image download */ 216 { DAVINCI_LPSC_UART2 }, /* console */ 217 { DAVINCI_LPSC_GPIO }, 218 }; 219 220 const int lpsc_size = ARRAY_SIZE(lpsc); 221 222 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK 223 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 224 #endif 225 226 #define REV_AM18X_EVM 0x100 227 228 /* 229 * get_board_rev() - setup to pass kernel board revision information 230 * Returns: 231 * bit[0-3] Maximum cpu clock rate supported by onboard SoC 232 * 0000b - 300 MHz 233 * 0001b - 372 MHz 234 * 0010b - 408 MHz 235 * 0011b - 456 MHz 236 */ 237 u32 get_board_rev(void) 238 { 239 char *s; 240 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; 241 u32 rev = 0; 242 243 s = getenv("maxcpuclk"); 244 if (s) 245 maxcpuclk = simple_strtoul(s, NULL, 10); 246 247 if (maxcpuclk >= 456000000) 248 rev = 3; 249 else if (maxcpuclk >= 408000000) 250 rev = 2; 251 else if (maxcpuclk >= 372000000) 252 rev = 1; 253 #ifdef CONFIG_DA850_AM18X_EVM 254 rev |= REV_AM18X_EVM; 255 #endif 256 return rev; 257 } 258 259 int board_early_init_f(void) 260 { 261 /* 262 * Power on required peripherals 263 * ARM does not have access by default to PSC0 and PSC1 264 * assuming here that the DSP bootloader has set the IOPU 265 * such that PSC access is available to ARM 266 */ 267 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 268 return 1; 269 270 return 0; 271 } 272 273 int board_init(void) 274 { 275 #ifdef CONFIG_USE_NOR 276 u32 val; 277 #endif 278 279 #ifndef CONFIG_USE_IRQ 280 irq_init(); 281 #endif 282 283 #ifdef CONFIG_NAND_DAVINCI 284 /* 285 * NAND CS setup - cycle counts based on da850evm NAND timings in the 286 * Linux kernel @ 25MHz EMIFA 287 */ 288 writel((DAVINCI_ABCR_WSETUP(0) | 289 DAVINCI_ABCR_WSTROBE(1) | 290 DAVINCI_ABCR_WHOLD(0) | 291 DAVINCI_ABCR_RSETUP(0) | 292 DAVINCI_ABCR_RSTROBE(1) | 293 DAVINCI_ABCR_RHOLD(0) | 294 DAVINCI_ABCR_TA(1) | 295 DAVINCI_ABCR_ASIZE_8BIT), 296 &davinci_emif_regs->ab2cr); /* CS3 */ 297 #endif 298 299 /* arch number of the board */ 300 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; 301 302 /* address of boot parameters */ 303 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; 304 305 /* setup the SUSPSRC for ARM to control emulation suspend */ 306 writel(readl(&davinci_syscfg_regs->suspsrc) & 307 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | 308 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | 309 DAVINCI_SYSCFG_SUSPSRC_UART2), 310 &davinci_syscfg_regs->suspsrc); 311 312 /* configure pinmux settings */ 313 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) 314 return 1; 315 316 #ifdef CONFIG_USE_NOR 317 /* Set the GPIO direction as output */ 318 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 319 320 /* Set the output as low */ 321 val = readl(GPIO_BANK0_REG_SET_ADDR); 322 val |= (0x01 << 11); 323 writel(val, GPIO_BANK0_REG_CLR_ADDR); 324 #endif 325 326 #ifdef CONFIG_DRIVER_TI_EMAC 327 davinci_emac_mii_mode_sel(HAS_RMII); 328 #endif /* CONFIG_DRIVER_TI_EMAC */ 329 330 /* enable the console UART */ 331 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 332 DAVINCI_UART_PWREMU_MGMT_UTRST), 333 &davinci_uart2_ctrl_regs->pwremu_mgmt); 334 335 return 0; 336 } 337 338 #ifdef CONFIG_DRIVER_TI_EMAC 339 340 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 341 /** 342 * rmii_hw_init 343 * 344 * DA850/OMAP-L138 EVM can interface to a daughter card for 345 * additional features. This card has an I2C GPIO Expander TCA6416 346 * to select the required functions like camera, RMII Ethernet, 347 * character LCD, video. 348 * 349 * Initialization of the expander involves configuring the 350 * polarity and direction of the ports. P07-P05 are used here. 351 * These ports are connected to a Mux chip which enables only one 352 * functionality at a time. 353 * 354 * For RMII phy to respond, the MII MDIO clock has to be disabled 355 * since both the PHY devices have address as zero. The MII MDIO 356 * clock is controlled via GPIO2[6]. 357 * 358 * This code is valid for Beta version of the hardware 359 */ 360 int rmii_hw_init(void) 361 { 362 const struct pinmux_config gpio_pins[] = { 363 { pinmux(6), 8, 1 } 364 }; 365 u_int8_t buf[2]; 366 unsigned int temp; 367 int ret; 368 369 /* PinMux for GPIO */ 370 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) 371 return 1; 372 373 /* I2C Exapnder configuration */ 374 /* Set polarity to non-inverted */ 375 buf[0] = 0x0; 376 buf[1] = 0x0; 377 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); 378 if (ret) { 379 printf("\nExpander @ 0x%02x write FAILED!!!\n", 380 CONFIG_SYS_I2C_EXPANDER_ADDR); 381 return ret; 382 } 383 384 /* Configure P07-P05 as outputs */ 385 buf[0] = 0x1f; 386 buf[1] = 0xff; 387 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); 388 if (ret) { 389 printf("\nExpander @ 0x%02x write FAILED!!!\n", 390 CONFIG_SYS_I2C_EXPANDER_ADDR); 391 } 392 393 /* For Ethernet RMII selection 394 * P07(SelA)=0 395 * P06(SelB)=1 396 * P05(SelC)=1 397 */ 398 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 399 printf("\nExpander @ 0x%02x read FAILED!!!\n", 400 CONFIG_SYS_I2C_EXPANDER_ADDR); 401 } 402 403 buf[0] &= 0x1f; 404 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); 405 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 406 printf("\nExpander @ 0x%02x write FAILED!!!\n", 407 CONFIG_SYS_I2C_EXPANDER_ADDR); 408 } 409 410 /* Set the output as high */ 411 temp = REG(GPIO_BANK2_REG_SET_ADDR); 412 temp |= (0x01 << 6); 413 REG(GPIO_BANK2_REG_SET_ADDR) = temp; 414 415 /* Set the GPIO direction as output */ 416 temp = REG(GPIO_BANK2_REG_DIR_ADDR); 417 temp &= ~(0x01 << 6); 418 REG(GPIO_BANK2_REG_DIR_ADDR) = temp; 419 420 return 0; 421 } 422 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ 423 424 /* 425 * Initializes on-board ethernet controllers. 426 */ 427 int board_eth_init(bd_t *bis) 428 { 429 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 430 /* Select RMII fucntion through the expander */ 431 if (rmii_hw_init()) 432 printf("RMII hardware init failed!!!\n"); 433 #endif 434 if (!davinci_emac_initialize()) { 435 printf("Error: Ethernet init failed!\n"); 436 return -1; 437 } 438 439 return 0; 440 } 441 #endif /* CONFIG_DRIVER_TI_EMAC */ 442