1*53193a4fSChristophe Leroy /*
2*53193a4fSChristophe Leroy * Copyright (C) 2010-2017 CS Systemes d'Information
3*53193a4fSChristophe Leroy * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
4*53193a4fSChristophe Leroy * Christophe Leroy <christophe.leroy@c-s.fr>
5*53193a4fSChristophe Leroy *
6*53193a4fSChristophe Leroy * SPDX-License-Identifier: GPL-2.0+
7*53193a4fSChristophe Leroy */
8*53193a4fSChristophe Leroy
9*53193a4fSChristophe Leroy #include <config.h>
10*53193a4fSChristophe Leroy #include <common.h>
11*53193a4fSChristophe Leroy #include <nand.h>
12*53193a4fSChristophe Leroy #include <asm/io.h>
13*53193a4fSChristophe Leroy
14*53193a4fSChristophe Leroy #define BIT_CLE ((unsigned short)0x0800)
15*53193a4fSChristophe Leroy #define BIT_ALE ((unsigned short)0x0400)
16*53193a4fSChristophe Leroy #define BIT_NCE ((unsigned short)0x1000)
17*53193a4fSChristophe Leroy
nand_hwcontrol(struct mtd_info * mtdinfo,int cmd,unsigned int ctrl)18*53193a4fSChristophe Leroy static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
19*53193a4fSChristophe Leroy {
20*53193a4fSChristophe Leroy struct nand_chip *this = mtdinfo->priv;
21*53193a4fSChristophe Leroy immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
22*53193a4fSChristophe Leroy unsigned short pddat = 0;
23*53193a4fSChristophe Leroy
24*53193a4fSChristophe Leroy /* The hardware control change */
25*53193a4fSChristophe Leroy if (ctrl & NAND_CTRL_CHANGE) {
26*53193a4fSChristophe Leroy pddat = in_be16(&immr->im_ioport.iop_pddat);
27*53193a4fSChristophe Leroy
28*53193a4fSChristophe Leroy /* Clearing ALE and CLE */
29*53193a4fSChristophe Leroy pddat &= ~(BIT_CLE | BIT_ALE);
30*53193a4fSChristophe Leroy
31*53193a4fSChristophe Leroy /* Driving NCE pin */
32*53193a4fSChristophe Leroy if (ctrl & NAND_NCE)
33*53193a4fSChristophe Leroy pddat &= ~BIT_NCE;
34*53193a4fSChristophe Leroy else
35*53193a4fSChristophe Leroy pddat |= BIT_NCE;
36*53193a4fSChristophe Leroy
37*53193a4fSChristophe Leroy /* Driving CLE and ALE pin */
38*53193a4fSChristophe Leroy if (ctrl & NAND_CLE)
39*53193a4fSChristophe Leroy pddat |= BIT_CLE;
40*53193a4fSChristophe Leroy if (ctrl & NAND_ALE)
41*53193a4fSChristophe Leroy pddat |= BIT_ALE;
42*53193a4fSChristophe Leroy
43*53193a4fSChristophe Leroy out_be16(&immr->im_ioport.iop_pddat, pddat);
44*53193a4fSChristophe Leroy }
45*53193a4fSChristophe Leroy
46*53193a4fSChristophe Leroy /* Writing the command */
47*53193a4fSChristophe Leroy if (cmd != NAND_CMD_NONE)
48*53193a4fSChristophe Leroy out_8(this->IO_ADDR_W, cmd);
49*53193a4fSChristophe Leroy }
50*53193a4fSChristophe Leroy
board_nand_init(struct nand_chip * nand)51*53193a4fSChristophe Leroy int board_nand_init(struct nand_chip *nand)
52*53193a4fSChristophe Leroy {
53*53193a4fSChristophe Leroy immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
54*53193a4fSChristophe Leroy
55*53193a4fSChristophe Leroy /* Set GPIO Port */
56*53193a4fSChristophe Leroy setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
57*53193a4fSChristophe Leroy clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
58*53193a4fSChristophe Leroy clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
59*53193a4fSChristophe Leroy
60*53193a4fSChristophe Leroy nand->chip_delay = 60;
61*53193a4fSChristophe Leroy nand->ecc.mode = NAND_ECC_SOFT;
62*53193a4fSChristophe Leroy nand->cmd_ctrl = nand_hwcontrol;
63*53193a4fSChristophe Leroy
64*53193a4fSChristophe Leroy return 0;
65*53193a4fSChristophe Leroy }
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