1 /* 2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 3 * Based on mx6qsabrelite.c file 4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 5 * Leo Sartre, <lsartre@adeneo-embedded.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/iomux.h> 15 #include <asm/arch/mx6-pins.h> 16 #include <asm/gpio.h> 17 #include <asm/imx-common/iomux-v3.h> 18 #include <asm/imx-common/boot_mode.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\ 25 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 26 27 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ 28 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 29 30 int dram_init(void) 31 { 32 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 33 34 return 0; 35 } 36 37 static iomux_v3_cfg_t const uart2_pads[] = { 38 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 39 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 40 }; 41 42 static iomux_v3_cfg_t const usdhc2_pads[] = { 43 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 44 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 45 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 46 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 47 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 48 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 49 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 50 }; 51 52 static iomux_v3_cfg_t const usdhc3_pads[] = { 53 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 54 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 55 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 56 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 57 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 58 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 59 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 60 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 61 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 62 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 63 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), 64 }; 65 66 static iomux_v3_cfg_t const usdhc4_pads[] = { 67 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 68 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 70 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 71 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 72 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 75 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 78 }; 79 80 static void setup_iomux_uart(void) 81 { 82 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 83 } 84 85 #ifdef CONFIG_FSL_ESDHC 86 static struct fsl_esdhc_cfg usdhc_cfg[] = { 87 {USDHC2_BASE_ADDR}, 88 {USDHC3_BASE_ADDR}, 89 {USDHC4_BASE_ADDR}, 90 }; 91 92 int board_mmc_getcd(struct mmc *mmc) 93 { 94 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 95 int ret = 0; 96 97 switch (cfg->esdhc_base) { 98 case USDHC2_BASE_ADDR: 99 gpio_direction_input(IMX_GPIO_NR(1, 4)); 100 ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); 101 break; 102 case USDHC3_BASE_ADDR: 103 ret = 1; /* eMMC is always present */ 104 break; 105 case USDHC4_BASE_ADDR: 106 gpio_direction_input(IMX_GPIO_NR(2, 6)); 107 ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); 108 break; 109 default: 110 printf("Bad USDHC interface\n"); 111 } 112 113 return ret; 114 } 115 116 int board_mmc_init(bd_t *bis) 117 { 118 s32 status = 0; 119 int i; 120 121 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 122 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 123 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 124 125 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 126 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 127 imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 128 129 for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) { 130 status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 131 if (status) 132 return status; 133 } 134 135 return 0; 136 } 137 #endif 138 139 int board_early_init_f(void) 140 { 141 setup_iomux_uart(); 142 143 return 0; 144 } 145 146 int board_init(void) 147 { 148 /* address of boot parameters */ 149 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 150 151 return 0; 152 } 153 154 int checkboard(void) 155 { 156 puts("Board: Conga-QEVAL QMX6 Quad\n"); 157 158 return 0; 159 } 160 161 #ifdef CONFIG_CMD_BMODE 162 static const struct boot_mode board_boot_modes[] = { 163 /* 4 bit bus width */ 164 {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)}, 165 {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)}, 166 {NULL, 0}, 167 }; 168 #endif 169 170 int misc_init_r(void) 171 { 172 #ifdef CONFIG_CMD_BMODE 173 add_board_boot_modes(board_boot_modes); 174 #endif 175 return 0; 176 } 177