139e37118SStephen Warren /* 239e37118SStephen Warren * (C) Copyright 2010-2012 339e37118SStephen Warren * NVIDIA Corporation <www.nvidia.com> 439e37118SStephen Warren * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 639e37118SStephen Warren */ 739e37118SStephen Warren 839e37118SStephen Warren #include <common.h> 939e37118SStephen Warren #include <asm/io.h> 10150c2493STom Warren #include <asm/arch/tegra.h> 1139e37118SStephen Warren #include <asm/arch/clock.h> 1239e37118SStephen Warren #include <asm/arch/funcmux.h> 1339e37118SStephen Warren #include <asm/arch/pinmux.h> 1439e37118SStephen Warren #include <asm/gpio.h> 15150c2493STom Warren #include <i2c.h> 1639e37118SStephen Warren pin_mux_usb(void)177155dc97SStephen Warrenvoid pin_mux_usb(void) 187155dc97SStephen Warren { 197155dc97SStephen Warren /* 207155dc97SStephen Warren * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO 217155dc97SStephen Warren * in the current device tree. 227155dc97SStephen Warren */ 23*70ad375eSStephen Warren pinmux_tristate_disable(PMUX_PINGRP_UAC); 247155dc97SStephen Warren } 2539e37118SStephen Warren pin_mux_spi(void)262db7b952SStephen Warrenvoid pin_mux_spi(void) 272db7b952SStephen Warren { 282db7b952SStephen Warren funcmux_select(PERIPH_ID_SPI1, FUNCMUX_SPI1_GMC_GMD); 292db7b952SStephen Warren } 302db7b952SStephen Warren 3139e37118SStephen Warren /* 3239e37118SStephen Warren * Routine: pin_mux_mmc 3339e37118SStephen Warren * Description: setup the pin muxes/tristate values for the SDMMC(s) 3439e37118SStephen Warren */ pin_mux_mmc(void)35c9aa831eSTom Warrenvoid pin_mux_mmc(void) 3639e37118SStephen Warren { 3739e37118SStephen Warren funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT); 3839e37118SStephen Warren funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); 3939e37118SStephen Warren 4039e37118SStephen Warren /* For CD GPIO PP1 */ 41*70ad375eSStephen Warren pinmux_tristate_disable(PMUX_PINGRP_DAP3); 4239e37118SStephen Warren } 43