1*076446f1SDmitry Lifshitz /*
2*076446f1SDmitry Lifshitz * SPL specific code for Compulab CM-T54 board
3*076446f1SDmitry Lifshitz *
4*076446f1SDmitry Lifshitz * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
5*076446f1SDmitry Lifshitz *
6*076446f1SDmitry Lifshitz * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
7*076446f1SDmitry Lifshitz *
8*076446f1SDmitry Lifshitz * SPDX-License-Identifier: GPL-2.0+
9*076446f1SDmitry Lifshitz */
10*076446f1SDmitry Lifshitz
11*076446f1SDmitry Lifshitz #include <asm/emif.h>
12*076446f1SDmitry Lifshitz
13*076446f1SDmitry Lifshitz const struct emif_regs emif_regs_ddr3_532_mhz_cm_t54 = {
14*076446f1SDmitry Lifshitz #if defined(CONFIG_DRAM_1G) || defined(CONFIG_DRAM_512M)
15*076446f1SDmitry Lifshitz .sdram_config_init = 0x618522B2,
16*076446f1SDmitry Lifshitz .sdram_config = 0x618522B2,
17*076446f1SDmitry Lifshitz #elif defined(CONFIG_DRAM_2G)
18*076446f1SDmitry Lifshitz .sdram_config_init = 0x618522BA,
19*076446f1SDmitry Lifshitz .sdram_config = 0x618522BA,
20*076446f1SDmitry Lifshitz #endif
21*076446f1SDmitry Lifshitz .sdram_config2 = 0x0,
22*076446f1SDmitry Lifshitz .ref_ctrl = 0x00001040,
23*076446f1SDmitry Lifshitz .sdram_tim1 = 0xEEEF36F3,
24*076446f1SDmitry Lifshitz .sdram_tim2 = 0x348F7FDA,
25*076446f1SDmitry Lifshitz .sdram_tim3 = 0x027F88A8,
26*076446f1SDmitry Lifshitz .read_idle_ctrl = 0x00050000,
27*076446f1SDmitry Lifshitz .zq_config = 0x1007190B,
28*076446f1SDmitry Lifshitz .temp_alert_config = 0x00000000,
29*076446f1SDmitry Lifshitz
30*076446f1SDmitry Lifshitz .emif_ddr_phy_ctlr_1_init = 0x0030400B,
31*076446f1SDmitry Lifshitz .emif_ddr_phy_ctlr_1 = 0x0034400B,
32*076446f1SDmitry Lifshitz .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
33*076446f1SDmitry Lifshitz .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
34*076446f1SDmitry Lifshitz .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
35*076446f1SDmitry Lifshitz .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
36*076446f1SDmitry Lifshitz .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
37*076446f1SDmitry Lifshitz .emif_rd_wr_lvl_rmp_win = 0x00000000,
38*076446f1SDmitry Lifshitz .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
39*076446f1SDmitry Lifshitz .emif_rd_wr_lvl_ctl = 0x00000000,
40*076446f1SDmitry Lifshitz .emif_rd_wr_exec_thresh = 0x40000305,
41*076446f1SDmitry Lifshitz };
42*076446f1SDmitry Lifshitz
43*076446f1SDmitry Lifshitz const struct dmm_lisa_map_regs lisa_map_cm_t54 = {
44*076446f1SDmitry Lifshitz .dmm_lisa_map_0 = 0x0,
45*076446f1SDmitry Lifshitz .dmm_lisa_map_1 = 0x0,
46*076446f1SDmitry Lifshitz
47*076446f1SDmitry Lifshitz #ifdef CONFIG_DRAM_2G
48*076446f1SDmitry Lifshitz .dmm_lisa_map_2 = 0x80740300,
49*076446f1SDmitry Lifshitz #elif defined(CONFIG_DRAM_1G)
50*076446f1SDmitry Lifshitz .dmm_lisa_map_2 = 0x80640300,
51*076446f1SDmitry Lifshitz #elif defined(CONFIG_DRAM_512M)
52*076446f1SDmitry Lifshitz .dmm_lisa_map_2 = 0x80500100,
53*076446f1SDmitry Lifshitz #endif
54*076446f1SDmitry Lifshitz .dmm_lisa_map_3 = 0x00000000,
55*076446f1SDmitry Lifshitz .is_ma_present = 0x1,
56*076446f1SDmitry Lifshitz };
57*076446f1SDmitry Lifshitz
emif_get_reg_dump(u32 emif_nr,const struct emif_regs ** regs)58*076446f1SDmitry Lifshitz void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
59*076446f1SDmitry Lifshitz {
60*076446f1SDmitry Lifshitz *regs = &emif_regs_ddr3_532_mhz_cm_t54;
61*076446f1SDmitry Lifshitz }
62*076446f1SDmitry Lifshitz
emif_get_dmm_regs(const struct dmm_lisa_map_regs ** dmm_lisa_regs)63*076446f1SDmitry Lifshitz void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
64*076446f1SDmitry Lifshitz {
65*076446f1SDmitry Lifshitz *dmm_lisa_regs = &lisa_map_cm_t54;
66*076446f1SDmitry Lifshitz }
67