1 /* 2 * Copyright (C) 2016 Compulab, Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <spl.h> 9 #include <asm/arch/clock.h> 10 #include <asm/arch/ddr_defs.h> 11 #include <asm/gpio.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 }; 16 const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 }; 17 const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 }; 18 const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 }; 19 20 const struct ctrl_ioregs ioregs_ddr3 = { 21 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 22 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 23 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 24 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 25 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 26 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 27 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 28 .emif_sdram_config_ext = 0x0143, 29 }; 30 31 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ 32 struct emif_regs ddr3_emif_regs = { 33 .sdram_config = 0x638413B2, 34 .ref_ctrl = 0x00000C30, 35 .sdram_tim1 = 0xEAAAD4DB, 36 .sdram_tim2 = 0x266B7FDA, 37 .sdram_tim3 = 0x107F8678, 38 .read_idle_ctrl = 0x00050000, 39 .zq_config = 0x50074BE4, 40 .temp_alert_config = 0x0, 41 .emif_ddr_phy_ctlr_1 = 0x0E004008, 42 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 43 .emif_ddr_ext_phy_ctrl_2 = 0x00000066, 44 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 45 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, 46 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, 47 .emif_rd_wr_exec_thresh = 0x80000405, 48 .emif_prio_class_serv_map = 0x80000001, 49 .emif_connect_id_serv_1_map = 0x80000094, 50 .emif_connect_id_serv_2_map = 0x00000000, 51 .emif_cos_config = 0x000FFFFF 52 }; 53 54 const u32 ext_phy_ctrl_const_base_ddr3[] = { 55 0x00000000, 56 0x00000044, 57 0x00000044, 58 0x00000046, 59 0x00000046, 60 0x00000000, 61 0x00000059, 62 0x00000077, 63 0x00000093, 64 0x000000A8, 65 0x00000000, 66 0x00000019, 67 0x00000037, 68 0x00000053, 69 0x00000068, 70 0x00000000, 71 0x0, 72 0x0, 73 0x40000000, 74 0x08102040 75 }; 76 77 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) 78 { 79 *regs = ext_phy_ctrl_const_base_ddr3; 80 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); 81 } 82 83 const struct dpll_params *get_dpll_ddr_params(void) 84 { 85 return &dpll_ddr; 86 } 87 88 const struct dpll_params *get_dpll_mpu_params(void) 89 { 90 return &dpll_mpu; 91 } 92 93 const struct dpll_params *get_dpll_core_params(void) 94 { 95 return &dpll_core; 96 } 97 98 const struct dpll_params *get_dpll_per_params(void) 99 { 100 return &dpll_per; 101 } 102 103 static void enable_vtt_regulator(void) 104 { 105 u32 temp; 106 107 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); 108 writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); 109 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 110 temp = temp & ~(GPIO_OE_ENABLE(7)); 111 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 112 } 113 114 void sdram_init(void) 115 { 116 unsigned long ram_size; 117 118 enable_vtt_regulator(); 119 config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); 120 ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); 121 if (ram_size == 0x80000000 || 122 ram_size == 0x40000000 || 123 ram_size == 0x20000000) 124 return; 125 126 ddr3_emif_regs.sdram_config = 0x638453B2; 127 config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); 128 ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); 129 if (ram_size == 0x08000000) 130 return; 131 132 hang(); 133 } 134 135