1 /* 2 * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il> 3 * 4 * Authors: Mike Rapoport <mike@compulab.co.il> 5 * Igor Grinberg <grinberg@compulab.co.il> 6 * 7 * Derived from omap3evm and Beagle Board by 8 * Manikandan Pillai <mani.pillai@ti.com> 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <status_led.h> 17 #include <netdev.h> 18 #include <net.h> 19 #include <i2c.h> 20 #include <usb.h> 21 #include <mmc.h> 22 #include <nand.h> 23 #include <twl4030.h> 24 #include <bmp_layout.h> 25 #include <linux/compiler.h> 26 27 #include <asm/io.h> 28 #include <asm/arch/mem.h> 29 #include <asm/arch/mux.h> 30 #include <asm/arch/mmc_host_def.h> 31 #include <asm/arch/sys_proto.h> 32 #include <asm/mach-types.h> 33 #include <asm/ehci-omap.h> 34 #include <asm/gpio.h> 35 36 #include "../common/common.h" 37 #include "../common/eeprom.h" 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 const omap3_sysinfo sysinfo = { 42 DDR_DISCRETE, 43 "CM-T3x board", 44 "NAND", 45 }; 46 47 static u32 gpmc_net_config[GPMC_MAX_REG] = { 48 NET_GPMC_CONFIG1, 49 NET_GPMC_CONFIG2, 50 NET_GPMC_CONFIG3, 51 NET_GPMC_CONFIG4, 52 NET_GPMC_CONFIG5, 53 NET_GPMC_CONFIG6, 54 0 55 }; 56 57 #ifdef CONFIG_LCD 58 #ifdef CONFIG_CMD_NAND 59 static int splash_load_from_nand(u32 bmp_load_addr) 60 { 61 struct bmp_header *bmp_hdr; 62 int res, splash_screen_nand_offset = 0x100000; 63 size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); 64 65 if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) 66 goto splash_address_too_high; 67 68 res = nand_read_skip_bad(&nand_info[nand_curr_device], 69 splash_screen_nand_offset, &bmp_header_size, 70 NULL, nand_info[nand_curr_device].size, 71 (u_char *)bmp_load_addr); 72 if (res < 0) 73 return res; 74 75 bmp_hdr = (struct bmp_header *)bmp_load_addr; 76 bmp_size = le32_to_cpu(bmp_hdr->file_size); 77 78 if (bmp_load_addr + bmp_size >= gd->start_addr_sp) 79 goto splash_address_too_high; 80 81 return nand_read_skip_bad(&nand_info[nand_curr_device], 82 splash_screen_nand_offset, &bmp_size, 83 NULL, nand_info[nand_curr_device].size, 84 (u_char *)bmp_load_addr); 85 86 splash_address_too_high: 87 printf("Error: splashimage address too high. Data overwrites U-Boot " 88 "and/or placed beyond DRAM boundaries.\n"); 89 90 return -1; 91 } 92 #else 93 static inline int splash_load_from_nand(void) 94 { 95 return -1; 96 } 97 #endif /* CONFIG_CMD_NAND */ 98 99 #ifdef CONFIG_SPL_BUILD 100 /* 101 * Routine: get_board_mem_timings 102 * Description: If we use SPL then there is no x-loader nor config header 103 * so we have to setup the DDR timings ourself on both banks. 104 */ 105 void get_board_mem_timings(struct board_sdrc_timings *timings) 106 { 107 timings->mr = MICRON_V_MR_165; 108 timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ 109 timings->ctrla = MICRON_V_ACTIMA_165; 110 timings->ctrlb = MICRON_V_ACTIMB_165; 111 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 112 } 113 #endif 114 115 int splash_screen_prepare(void) 116 { 117 char *env_splashimage_value; 118 u32 bmp_load_addr; 119 120 env_splashimage_value = getenv("splashimage"); 121 if (env_splashimage_value == NULL) 122 return -1; 123 124 bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); 125 if (bmp_load_addr == 0) { 126 printf("Error: bad splashimage address specified\n"); 127 return -1; 128 } 129 130 return splash_load_from_nand(bmp_load_addr); 131 } 132 #endif /* CONFIG_LCD */ 133 134 /* 135 * Routine: board_init 136 * Description: hardware init. 137 */ 138 int board_init(void) 139 { 140 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 141 142 /* board id for Linux */ 143 if (get_cpu_family() == CPU_OMAP34XX) 144 gd->bd->bi_arch_number = MACH_TYPE_CM_T35; 145 else 146 gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; 147 148 /* boot param addr */ 149 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 150 151 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) 152 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); 153 #endif 154 155 return 0; 156 } 157 158 /* 159 * Routine: get_board_rev 160 * Description: read system revision 161 */ 162 u32 get_board_rev(void) 163 { 164 return cl_eeprom_get_board_rev(); 165 }; 166 167 int misc_init_r(void) 168 { 169 cl_print_pcb_info(); 170 dieid_num_r(); 171 172 return 0; 173 } 174 175 /* 176 * Routine: set_muxconf_regs 177 * Description: Setting up the configuration Mux registers specific to the 178 * hardware. Many pins need to be moved from protect to primary 179 * mode. 180 */ 181 static void cm_t3x_set_common_muxconf(void) 182 { 183 /* SDRC */ 184 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ 185 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ 186 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ 187 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ 188 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ 189 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ 190 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ 191 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ 192 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ 193 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ 194 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ 195 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ 196 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ 197 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ 198 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ 199 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ 200 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ 201 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ 202 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ 203 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ 204 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ 205 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ 206 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ 207 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ 208 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ 209 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ 210 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ 211 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ 212 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ 213 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ 214 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ 215 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ 216 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ 217 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ 218 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ 219 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ 220 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ 221 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ 222 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ 223 224 /* GPMC */ 225 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ 226 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ 227 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ 228 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ 229 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ 230 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ 231 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ 232 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ 233 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ 234 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ 235 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ 236 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ 237 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ 238 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ 239 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ 240 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ 241 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ 242 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ 243 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ 244 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ 245 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ 246 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ 247 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ 248 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ 249 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ 250 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ 251 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ 252 253 /* SB-T35 Ethernet */ 254 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ 255 256 /* DVI enable */ 257 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ 258 259 /* DataImage backlight */ 260 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ 261 262 /* CM-T3x Ethernet */ 263 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ 264 MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ 265 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ 266 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ 267 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ 268 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ 269 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ 270 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ 271 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ 272 273 /* DSS */ 274 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ 275 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ 276 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ 277 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ 278 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ 279 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ 280 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ 281 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ 282 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ 283 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ 284 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ 285 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ 286 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ 287 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ 288 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ 289 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ 290 291 /* serial interface */ 292 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ 293 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ 294 295 /* mUSB */ 296 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ 297 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ 298 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ 299 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ 300 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ 301 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ 302 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ 303 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ 304 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ 305 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ 306 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ 307 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ 308 309 /* USB EHCI */ 310 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ 311 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ 312 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ 313 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ 314 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ 315 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ 316 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ 317 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ 318 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ 319 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ 320 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ 321 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ 322 323 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ 324 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ 325 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ 326 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ 327 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ 328 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ 329 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ 330 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ 331 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ 332 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ 333 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ 334 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ 335 336 /* SB_T35_USB_HUB_RESET_GPIO */ 337 MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ 338 339 /* I2C1 */ 340 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ 341 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ 342 /* I2C2 */ 343 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ 344 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ 345 /* I2C3 */ 346 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ 347 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ 348 349 /* control and debug */ 350 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ 351 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ 352 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ 353 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ 354 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ 355 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ 356 MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/ 357 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ 358 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ 359 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ 360 361 /* MMC1 */ 362 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ 363 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ 364 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ 365 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ 366 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ 367 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ 368 369 /* SPI */ 370 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ 371 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ 372 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ 373 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ 374 375 /* display controls */ 376 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ 377 } 378 379 static void cm_t35_set_muxconf(void) 380 { 381 /* DSS */ 382 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ 383 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ 384 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ 385 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ 386 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ 387 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ 388 389 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ 390 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ 391 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ 392 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ 393 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ 394 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ 395 396 /* MMC1 */ 397 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ 398 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ 399 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ 400 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ 401 } 402 403 static void cm_t3730_set_muxconf(void) 404 { 405 /* DSS */ 406 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/ 407 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/ 408 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/ 409 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/ 410 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/ 411 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/ 412 413 MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/ 414 MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/ 415 MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/ 416 MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/ 417 MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/ 418 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/ 419 } 420 421 void set_muxconf_regs(void) 422 { 423 cm_t3x_set_common_muxconf(); 424 425 if (get_cpu_family() == CPU_OMAP34XX) 426 cm_t35_set_muxconf(); 427 else 428 cm_t3730_set_muxconf(); 429 } 430 431 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 432 #define SB_T35_WP_GPIO 59 433 434 int board_mmc_getcd(struct mmc *mmc) 435 { 436 u8 val; 437 438 if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val)) 439 return -1; 440 441 return !(val & 1); 442 } 443 444 int board_mmc_init(bd_t *bis) 445 { 446 return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO); 447 } 448 #endif 449 450 /* 451 * Routine: setup_net_chip_gmpc 452 * Description: Setting up the configuration GPMC registers specific to the 453 * Ethernet hardware. 454 */ 455 static void setup_net_chip_gmpc(void) 456 { 457 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 458 459 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], 460 CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); 461 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], 462 SB_T35_SMC911X_BASE, GPMC_SIZE_16M); 463 464 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 465 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 466 467 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 468 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 469 470 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 471 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 472 &ctrl_base->gpmc_nadv_ale); 473 } 474 475 #ifdef CONFIG_SYS_I2C_OMAP34XX 476 /* 477 * Routine: reset_net_chip 478 * Description: reset the Ethernet controller via TPS65930 GPIO 479 */ 480 static void reset_net_chip(void) 481 { 482 /* Set GPIO1 of TPS65930 as output */ 483 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, 484 0x02); 485 /* Send a pulse on the GPIO pin */ 486 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 487 0x02); 488 udelay(1); 489 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09, 490 0x02); 491 mdelay(40); 492 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 493 0x02); 494 mdelay(1); 495 } 496 #else 497 static inline void reset_net_chip(void) {} 498 #endif 499 500 #ifdef CONFIG_SMC911X 501 /* 502 * Routine: handle_mac_address 503 * Description: prepare MAC address for on-board Ethernet. 504 */ 505 static int handle_mac_address(void) 506 { 507 unsigned char enetaddr[6]; 508 int rc; 509 510 rc = eth_getenv_enetaddr("ethaddr", enetaddr); 511 if (rc) 512 return 0; 513 514 rc = cl_eeprom_read_mac_addr(enetaddr); 515 if (rc) 516 return rc; 517 518 if (!is_valid_ether_addr(enetaddr)) 519 return -1; 520 521 return eth_setenv_enetaddr("ethaddr", enetaddr); 522 } 523 524 525 /* 526 * Routine: board_eth_init 527 * Description: initialize module and base-board Ethernet chips 528 */ 529 int board_eth_init(bd_t *bis) 530 { 531 int rc = 0, rc1 = 0; 532 533 setup_net_chip_gmpc(); 534 reset_net_chip(); 535 536 rc1 = handle_mac_address(); 537 if (rc1) 538 printf("No MAC address found! "); 539 540 rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); 541 if (rc1 > 0) 542 rc++; 543 544 rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); 545 if (rc1 > 0) 546 rc++; 547 548 return rc; 549 } 550 #endif 551 552 void __weak get_board_serial(struct tag_serialnr *serialnr) 553 { 554 /* 555 * This corresponds to what happens when we can communicate with the 556 * eeprom but don't get a valid board serial value. 557 */ 558 serialnr->low = 0; 559 serialnr->high = 0; 560 }; 561 562 #ifdef CONFIG_USB_EHCI_OMAP 563 struct omap_usbhs_board_data usbhs_bdata = { 564 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 565 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 566 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 567 }; 568 569 #define SB_T35_USB_HUB_RESET_GPIO 167 570 int ehci_hcd_init(int index, enum usb_init_type init, 571 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 572 { 573 u8 val; 574 int offset; 575 576 cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); 577 578 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; 579 twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); 580 /* Set GPIO6 and GPIO7 of TPS65930 as output */ 581 val |= 0xC0; 582 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); 583 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; 584 /* Take both PHYs out of reset */ 585 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); 586 udelay(1); 587 588 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 589 } 590 591 int ehci_hcd_stop(void) 592 { 593 cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); 594 return omap_ehci_hcd_stop(); 595 } 596 #endif /* CONFIG_USB_EHCI_OMAP */ 597