1 /* 2 * Board functions for Compulab CM-FX6 board 3 * 4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ 5 * 6 * Author: Nikita Kiryanov <nikita@compulab.co.il> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <fsl_esdhc.h> 14 #include <miiphy.h> 15 #include <netdev.h> 16 #include <errno.h> 17 #include <usb.h> 18 #include <fdt_support.h> 19 #include <sata.h> 20 #include <splash.h> 21 #include <asm/arch/crm_regs.h> 22 #include <asm/arch/sys_proto.h> 23 #include <asm/arch/iomux.h> 24 #include <asm/arch/mxc_hdmi.h> 25 #include <asm/imx-common/mxc_i2c.h> 26 #include <asm/imx-common/sata.h> 27 #include <asm/imx-common/video.h> 28 #include <asm/io.h> 29 #include <asm/gpio.h> 30 #include <dm/platform_data/serial_mxc.h> 31 #include "common.h" 32 #include "../common/eeprom.h" 33 #include "../common/common.h" 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifdef CONFIG_SPLASH_SCREEN 38 static struct splash_location cm_fx6_splash_locations[] = { 39 { 40 .name = "sf", 41 .storage = SPLASH_STORAGE_SF, 42 .flags = SPLASH_STORAGE_RAW, 43 .offset = 0x100000, 44 }, 45 }; 46 47 int splash_screen_prepare(void) 48 { 49 return splash_source_load(cm_fx6_splash_locations, 50 ARRAY_SIZE(cm_fx6_splash_locations)); 51 } 52 #endif 53 54 #ifdef CONFIG_IMX_HDMI 55 static void cm_fx6_enable_hdmi(struct display_info_t const *dev) 56 { 57 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 58 imx_setup_hdmi(); 59 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); 60 imx_enable_hdmi_phy(); 61 } 62 63 static struct display_info_t preset_hdmi_1024X768 = { 64 .bus = -1, 65 .addr = 0, 66 .pixfmt = IPU_PIX_FMT_RGB24, 67 .enable = cm_fx6_enable_hdmi, 68 .mode = { 69 .name = "HDMI", 70 .refresh = 60, 71 .xres = 1024, 72 .yres = 768, 73 .pixclock = 40385, 74 .left_margin = 220, 75 .right_margin = 40, 76 .upper_margin = 21, 77 .lower_margin = 7, 78 .hsync_len = 60, 79 .vsync_len = 10, 80 .sync = FB_SYNC_EXT, 81 .vmode = FB_VMODE_NONINTERLACED, 82 } 83 }; 84 85 static void cm_fx6_setup_display(void) 86 { 87 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 88 89 enable_ipu_clock(); 90 clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); 91 } 92 93 int board_video_skip(void) 94 { 95 int ret; 96 struct display_info_t *preset; 97 char const *panel = getenv("displaytype"); 98 99 if (!panel) /* Also accept panel for backward compatibility */ 100 panel = getenv("panel"); 101 102 if (!panel) 103 return -ENOENT; 104 105 if (!strcmp(panel, "HDMI")) 106 preset = &preset_hdmi_1024X768; 107 else 108 return -EINVAL; 109 110 ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt); 111 if (ret) { 112 printf("Can't init display %s: %d\n", preset->mode.name, ret); 113 return ret; 114 } 115 116 preset->enable(preset); 117 printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres, 118 preset->mode.yres); 119 120 return 0; 121 } 122 #else 123 static inline void cm_fx6_setup_display(void) {} 124 #endif /* CONFIG_VIDEO_IPUV3 */ 125 126 #ifdef CONFIG_DWC_AHSATA 127 static int cm_fx6_issd_gpios[] = { 128 /* The order of the GPIOs in the array is important! */ 129 CM_FX6_SATA_LDO_EN, 130 CM_FX6_SATA_PHY_SLP, 131 CM_FX6_SATA_NRSTDLY, 132 CM_FX6_SATA_PWREN, 133 CM_FX6_SATA_NSTANDBY1, 134 CM_FX6_SATA_NSTANDBY2, 135 }; 136 137 static void cm_fx6_sata_power(int on) 138 { 139 int i; 140 141 if (!on) { /* tell the iSSD that the power will be removed */ 142 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1); 143 mdelay(10); 144 } 145 146 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { 147 gpio_direction_output(cm_fx6_issd_gpios[i], on); 148 udelay(100); 149 } 150 151 if (!on) /* for compatibility lower the power loss interrupt */ 152 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); 153 } 154 155 static iomux_v3_cfg_t const sata_pads[] = { 156 /* SATA PWR */ 157 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), 158 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), 159 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), 160 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 161 /* SATA CTRL */ 162 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), 163 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), 164 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), 165 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 166 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), 167 }; 168 169 static int cm_fx6_setup_issd(void) 170 { 171 int ret, i; 172 173 SETUP_IOMUX_PADS(sata_pads); 174 175 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { 176 ret = gpio_request(cm_fx6_issd_gpios[i], "sata"); 177 if (ret) 178 return ret; 179 } 180 181 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int"); 182 if (ret) 183 return ret; 184 185 return 0; 186 } 187 188 #define CM_FX6_SATA_INIT_RETRIES 10 189 int sata_initialize(void) 190 { 191 int err, i; 192 193 /* Make sure this gpio has logical 0 value */ 194 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); 195 udelay(100); 196 cm_fx6_sata_power(1); 197 198 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) { 199 err = setup_sata(); 200 if (err) { 201 printf("SATA setup failed: %d\n", err); 202 return err; 203 } 204 205 udelay(100); 206 207 err = __sata_initialize(); 208 if (!err) 209 break; 210 211 /* There is no device on the SATA port */ 212 if (sata_port_status(0, 0) == 0) 213 break; 214 215 /* There's a device, but link not established. Retry */ 216 } 217 218 return err; 219 } 220 221 int sata_stop(void) 222 { 223 __sata_stop(); 224 cm_fx6_sata_power(0); 225 mdelay(250); 226 227 return 0; 228 } 229 #else 230 static int cm_fx6_setup_issd(void) { return 0; } 231 #endif 232 233 #ifdef CONFIG_SYS_I2C_MXC 234 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 235 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 236 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 237 238 I2C_PADS(i2c0_pads, 239 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 240 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL), 241 IMX_GPIO_NR(3, 21), 242 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 243 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL), 244 IMX_GPIO_NR(3, 28)); 245 246 I2C_PADS(i2c1_pads, 247 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 248 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), 249 IMX_GPIO_NR(4, 12), 250 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 251 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), 252 IMX_GPIO_NR(4, 13)); 253 254 I2C_PADS(i2c2_pads, 255 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 256 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL), 257 IMX_GPIO_NR(1, 3), 258 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 259 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL), 260 IMX_GPIO_NR(1, 6)); 261 262 263 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads) 264 { 265 int ret; 266 267 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads); 268 if (ret) 269 printf("Warning: I2C%d setup failed: %d\n", busnum, ret); 270 271 return ret; 272 } 273 274 static int cm_fx6_setup_i2c(void) 275 { 276 int ret = 0, err; 277 278 /* i2c<x>_pads are wierd macro variables; we can't use an array */ 279 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads)); 280 if (err) 281 ret = err; 282 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads)); 283 if (err) 284 ret = err; 285 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads)); 286 if (err) 287 ret = err; 288 289 return ret; 290 } 291 #else 292 static int cm_fx6_setup_i2c(void) { return 0; } 293 #endif 294 295 #ifdef CONFIG_USB_EHCI_MX6 296 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ 297 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 298 PAD_CTL_HYS | PAD_CTL_SRE_SLOW) 299 #define MX6_USBNC_BASEADDR 0x2184800 300 #define USBNC_USB_H1_PWR_POL (1 << 9) 301 302 static int cm_fx6_setup_usb_host(void) 303 { 304 int err; 305 306 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst"); 307 if (err) 308 return err; 309 310 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)); 311 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)); 312 313 return 0; 314 } 315 316 static int cm_fx6_setup_usb_otg(void) 317 { 318 int err; 319 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 320 321 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr"); 322 if (err) { 323 printf("USB OTG pwr gpio request failed: %d\n", err); 324 return err; 325 } 326 327 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)); 328 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID | 329 MUX_PAD_CTRL(WEAK_PULLDOWN)); 330 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK); 331 /* disable ext. charger detect, or it'll affect signal quality at dp. */ 332 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0); 333 } 334 335 int board_usb_phy_mode(int port) 336 { 337 return USB_INIT_HOST; 338 } 339 340 int board_ehci_hcd_init(int port) 341 { 342 int ret; 343 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4); 344 345 /* Only 1 host controller in use. port 0 is OTG & needs no attention */ 346 if (port != 1) 347 return 0; 348 349 /* Set PWR polarity to match power switch's enable polarity */ 350 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL); 351 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0); 352 if (ret) 353 return ret; 354 355 udelay(10); 356 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1); 357 if (ret) 358 return ret; 359 360 mdelay(1); 361 362 return 0; 363 } 364 365 int board_ehci_power(int port, int on) 366 { 367 if (port == 0) 368 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on); 369 370 return 0; 371 } 372 #else 373 static int cm_fx6_setup_usb_otg(void) { return 0; } 374 static int cm_fx6_setup_usb_host(void) { return 0; } 375 #endif 376 377 #ifdef CONFIG_FEC_MXC 378 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 379 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 380 381 static int mx6_rgmii_rework(struct phy_device *phydev) 382 { 383 unsigned short val; 384 385 /* Ar8031 phy SmartEEE feature cause link status generates glitch, 386 * which cause ethernet link down/up issue, so disable SmartEEE 387 */ 388 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); 389 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); 390 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); 391 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 392 val &= ~(0x1 << 8); 393 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 394 395 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 396 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 397 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 398 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 399 400 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 401 val &= 0xffe3; 402 val |= 0x18; 403 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 404 405 /* introduce tx clock delay */ 406 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 407 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 408 val |= 0x0100; 409 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 410 411 return 0; 412 } 413 414 int board_phy_config(struct phy_device *phydev) 415 { 416 mx6_rgmii_rework(phydev); 417 418 if (phydev->drv->config) 419 return phydev->drv->config(phydev); 420 421 return 0; 422 } 423 424 static iomux_v3_cfg_t const enet_pads[] = { 425 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 426 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 427 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 428 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 429 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 430 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 431 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 432 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 433 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 434 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 435 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 436 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 437 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)), 438 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)), 439 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)), 440 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | 441 MUX_PAD_CTRL(ENET_PAD_CTRL)), 442 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | 443 MUX_PAD_CTRL(ENET_PAD_CTRL)), 444 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | 445 MUX_PAD_CTRL(ENET_PAD_CTRL)), 446 }; 447 448 static int handle_mac_address(char *env_var, uint eeprom_bus) 449 { 450 unsigned char enetaddr[6]; 451 int rc; 452 453 rc = eth_getenv_enetaddr(env_var, enetaddr); 454 if (rc) 455 return 0; 456 457 rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus); 458 if (rc) 459 return rc; 460 461 if (!is_valid_ethaddr(enetaddr)) 462 return -1; 463 464 return eth_setenv_enetaddr(env_var, enetaddr); 465 } 466 467 #define SB_FX6_I2C_EEPROM_BUS 0 468 #define NO_MAC_ADDR "No MAC address found for %s\n" 469 int board_eth_init(bd_t *bis) 470 { 471 int err; 472 473 if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS)) 474 printf(NO_MAC_ADDR, "primary NIC"); 475 476 if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS)) 477 printf(NO_MAC_ADDR, "secondary NIC"); 478 479 SETUP_IOMUX_PADS(enet_pads); 480 /* phy reset */ 481 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst"); 482 if (err) 483 printf("Etnernet NRST gpio request failed: %d\n", err); 484 gpio_direction_output(CM_FX6_ENET_NRST, 0); 485 udelay(500); 486 gpio_set_value(CM_FX6_ENET_NRST, 1); 487 enable_enet_clk(1); 488 return cpu_eth_init(bis); 489 } 490 #endif 491 492 #ifdef CONFIG_NAND_MXS 493 static iomux_v3_cfg_t const nand_pads[] = { 494 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), 495 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), 496 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 497 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 498 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 499 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), 500 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 501 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), 502 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 503 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), 504 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 505 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), 506 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 507 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 508 }; 509 510 static void cm_fx6_setup_gpmi_nand(void) 511 { 512 SETUP_IOMUX_PADS(nand_pads); 513 /* Enable clock roots */ 514 enable_usdhc_clk(1, 3); 515 enable_usdhc_clk(1, 4); 516 517 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) | 518 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) | 519 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0)); 520 } 521 #else 522 static void cm_fx6_setup_gpmi_nand(void) {} 523 #endif 524 525 #ifdef CONFIG_FSL_ESDHC 526 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 527 {USDHC1_BASE_ADDR}, 528 {USDHC2_BASE_ADDR}, 529 {USDHC3_BASE_ADDR}, 530 }; 531 532 static enum mxc_clock usdhc_clk[3] = { 533 MXC_ESDHC_CLK, 534 MXC_ESDHC2_CLK, 535 MXC_ESDHC3_CLK, 536 }; 537 538 int board_mmc_init(bd_t *bis) 539 { 540 int i; 541 542 cm_fx6_set_usdhc_iomux(); 543 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 544 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]); 545 usdhc_cfg[i].max_bus_width = 4; 546 fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 547 enable_usdhc_clk(1, i); 548 } 549 550 return 0; 551 } 552 #endif 553 554 #ifdef CONFIG_MXC_SPI 555 int cm_fx6_setup_ecspi(void) 556 { 557 cm_fx6_set_ecspi_iomux(); 558 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0"); 559 } 560 #else 561 int cm_fx6_setup_ecspi(void) { return 0; } 562 #endif 563 564 #ifdef CONFIG_OF_BOARD_SETUP 565 #define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/" 566 int ft_board_setup(void *blob, bd_t *bd) 567 { 568 u32 baseboard_rev; 569 int nodeoffset; 570 uint8_t enetaddr[6]; 571 char baseboard_name[16]; 572 int err; 573 574 /* MAC addr */ 575 if (eth_getenv_enetaddr("ethaddr", enetaddr)) { 576 fdt_find_and_setprop(blob, 577 "/soc/aips-bus@02100000/ethernet@02188000", 578 "local-mac-address", enetaddr, 6, 1); 579 } 580 581 if (eth_getenv_enetaddr("eth1addr", enetaddr)) { 582 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address", 583 enetaddr, 6, 1); 584 } 585 586 baseboard_rev = cl_eeprom_get_board_rev(0); 587 err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0); 588 if (err || baseboard_rev == 0) 589 return 0; /* Assume not an early revision SB-FX6m baseboard */ 590 591 if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) { 592 fdt_shrink_to_minimum(blob); /* Make room for new properties */ 593 nodeoffset = fdt_path_offset(blob, USDHC3_PATH); 594 fdt_delprop(blob, nodeoffset, "cd-gpios"); 595 fdt_find_and_setprop(blob, USDHC3_PATH, "non-removable", 596 NULL, 0, 1); 597 fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend", 598 NULL, 0, 1); 599 } 600 601 return 0; 602 } 603 #endif 604 605 int board_init(void) 606 { 607 int ret; 608 609 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 610 cm_fx6_setup_gpmi_nand(); 611 612 ret = cm_fx6_setup_ecspi(); 613 if (ret) 614 printf("Warning: ECSPI setup failed: %d\n", ret); 615 616 ret = cm_fx6_setup_usb_otg(); 617 if (ret) 618 printf("Warning: USB OTG setup failed: %d\n", ret); 619 620 ret = cm_fx6_setup_usb_host(); 621 if (ret) 622 printf("Warning: USB host setup failed: %d\n", ret); 623 624 /* 625 * cm-fx6 may have iSSD not assembled and in this case it has 626 * bypasses for a (m)SATA socket on the baseboard. The socketed 627 * device is not controlled by those GPIOs. So just print a warning 628 * if the setup fails. 629 */ 630 ret = cm_fx6_setup_issd(); 631 if (ret) 632 printf("Warning: iSSD setup failed: %d\n", ret); 633 634 /* Warn on failure but do not abort boot */ 635 ret = cm_fx6_setup_i2c(); 636 if (ret) 637 printf("Warning: I2C setup failed: %d\n", ret); 638 639 cm_fx6_setup_display(); 640 641 return 0; 642 } 643 644 int checkboard(void) 645 { 646 puts("Board: CM-FX6\n"); 647 return 0; 648 } 649 650 int misc_init_r(void) 651 { 652 cl_print_pcb_info(); 653 654 return 0; 655 } 656 657 void dram_init_banksize(void) 658 { 659 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 660 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 661 662 switch (gd->ram_size) { 663 case 0x10000000: /* DDR_16BIT_256MB */ 664 gd->bd->bi_dram[0].size = 0x10000000; 665 gd->bd->bi_dram[1].size = 0; 666 break; 667 case 0x20000000: /* DDR_32BIT_512MB */ 668 gd->bd->bi_dram[0].size = 0x20000000; 669 gd->bd->bi_dram[1].size = 0; 670 break; 671 case 0x40000000: 672 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ 673 gd->bd->bi_dram[0].size = 0x20000000; 674 gd->bd->bi_dram[1].size = 0x20000000; 675 } else { /* DDR_64BIT_1GB */ 676 gd->bd->bi_dram[0].size = 0x40000000; 677 gd->bd->bi_dram[1].size = 0; 678 } 679 break; 680 case 0x80000000: /* DDR_64BIT_2GB */ 681 gd->bd->bi_dram[0].size = 0x40000000; 682 gd->bd->bi_dram[1].size = 0x40000000; 683 break; 684 case 0xEFF00000: /* DDR_64BIT_4GB */ 685 gd->bd->bi_dram[0].size = 0x70000000; 686 gd->bd->bi_dram[1].size = 0x7FF00000; 687 break; 688 } 689 } 690 691 int dram_init(void) 692 { 693 gd->ram_size = imx_ddr_size(); 694 switch (gd->ram_size) { 695 case 0x10000000: 696 case 0x20000000: 697 case 0x40000000: 698 case 0x80000000: 699 break; 700 case 0xF0000000: 701 gd->ram_size -= 0x100000; 702 break; 703 default: 704 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size); 705 return -1; 706 } 707 708 return 0; 709 } 710 711 u32 get_board_rev(void) 712 { 713 return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS); 714 } 715 716 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = { 717 .reg = (struct mxc_uart *)UART4_BASE, 718 }; 719 720 U_BOOT_DEVICE(cm_fx6_serial) = { 721 .name = "serial_mxc", 722 .platdata = &cm_fx6_mxc_serial_plat, 723 }; 724