xref: /rk3399_rockchip-uboot/board/cei/cei-tk1-som/cei-tk1-som.c (revision e3f44f5c891da635123b734a056dd1275eb34d83)
1b6152676SPeter Chubb /*
2b6152676SPeter Chubb  * (C) Copyright 2014
3b6152676SPeter Chubb  * NVIDIA Corporation <www.nvidia.com>
4b6152676SPeter Chubb  *
5b6152676SPeter Chubb  * SPDX-License-Identifier:     GPL-2.0+
6b6152676SPeter Chubb  */
7b6152676SPeter Chubb 
8b6152676SPeter Chubb #include <common.h>
9b6152676SPeter Chubb #include <power/as3722.h>
10b6152676SPeter Chubb 
11b6152676SPeter Chubb #include <asm/arch/gpio.h>
12b6152676SPeter Chubb #include <asm/arch/pinmux.h>
13b6152676SPeter Chubb 
14b6152676SPeter Chubb #include "pinmux-config-cei-tk1-som.h"
15b6152676SPeter Chubb 
16b6152676SPeter Chubb DECLARE_GLOBAL_DATA_PTR;
17b6152676SPeter Chubb 
18b6152676SPeter Chubb /*
19b6152676SPeter Chubb  * Routine: pinmux_init
20b6152676SPeter Chubb  * Description: Do individual peripheral pinmux configs
21b6152676SPeter Chubb  */
pinmux_init(void)22b6152676SPeter Chubb void pinmux_init(void)
23b6152676SPeter Chubb {
24b6152676SPeter Chubb 	pinmux_clear_tristate_input_clamping();
25b6152676SPeter Chubb 
26b6152676SPeter Chubb 	gpio_config_table(cei_tk1_som_gpio_inits,
27b6152676SPeter Chubb 			  ARRAY_SIZE(cei_tk1_som_gpio_inits));
28b6152676SPeter Chubb 
29b6152676SPeter Chubb 	pinmux_config_pingrp_table(cei_tk1_som_pingrps,
30b6152676SPeter Chubb 				   ARRAY_SIZE(cei_tk1_som_pingrps));
31b6152676SPeter Chubb 
32b6152676SPeter Chubb 	pinmux_config_drvgrp_table(cei_tk1_som_drvgrps,
33b6152676SPeter Chubb 				   ARRAY_SIZE(cei_tk1_som_drvgrps));
34b6152676SPeter Chubb 
35b6152676SPeter Chubb 	pinmux_config_mipipadctrlgrp_table(cei_tk1_som_mipipadctrlgrps,
36b6152676SPeter Chubb                                            ARRAY_SIZE(cei_tk1_som_mipipadctrlgrps));
37b6152676SPeter Chubb }
38b6152676SPeter Chubb 
39b6152676SPeter Chubb #ifdef CONFIG_PCI_TEGRA
tegra_pcie_board_init(void)40b6152676SPeter Chubb int tegra_pcie_board_init(void)
41b6152676SPeter Chubb {
42*e3f44f5cSSimon Glass /* TODO: Convert to driver model
43b6152676SPeter Chubb 	struct udevice *pmic;
44b6152676SPeter Chubb 	int err;
45b6152676SPeter Chubb 
46b6152676SPeter Chubb 	err = as3722_init(&pmic);
47b6152676SPeter Chubb 	if (err) {
48b6152676SPeter Chubb 		error("failed to initialize AS3722 PMIC: %d\n", err);
49b6152676SPeter Chubb 		return err;
50b6152676SPeter Chubb 	}
51b6152676SPeter Chubb 
52b6152676SPeter Chubb 	err = as3722_sd_enable(pmic, 4);
53b6152676SPeter Chubb 	if (err < 0) {
54b6152676SPeter Chubb 		error("failed to enable SD4: %d\n", err);
55b6152676SPeter Chubb 		return err;
56b6152676SPeter Chubb 	}
57b6152676SPeter Chubb 
58b6152676SPeter Chubb 	err = as3722_sd_set_voltage(pmic, 4, 0x24);
59b6152676SPeter Chubb 	if (err < 0) {
60b6152676SPeter Chubb 		error("failed to set SD4 voltage: %d\n", err);
61b6152676SPeter Chubb 		return err;
62b6152676SPeter Chubb 	}
63*e3f44f5cSSimon Glass */
64b6152676SPeter Chubb 
65b6152676SPeter Chubb 	return 0;
66b6152676SPeter Chubb }
67b6152676SPeter Chubb #endif /* PCI */
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